jianzhong.map.qmsg

最基本的vhdl程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 24 09:21:43 2009 " "Info: Processing started: Sun May 24 09:21:43 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jianzhong -c jianzhong " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jianzhong -c jianzhong" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jianzhong.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file jianzhong.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jianzhong-zhong " "Info: Found design unit 1: jianzhong-zhong" {  } { { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 6 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 jianzhong " "Info: Found entity 1: jianzhong" {  } { { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jianzhong " "Info: Elaborating entity \"jianzhong\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "f jianzhong.vhd(11) " "Warning (10631): VHDL Process Statement warning at jianzhong.vhd(11): inferring latch(es) for signal or variable \"f\", which holds its previous value in one or more paths through the process" {  } { { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "f\[0\] jianzhong.vhd(11) " "Info (10041): Inferred latch for \"f\[0\]\" at jianzhong.vhd(11)" {  } { { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "f\[1\] jianzhong.vhd(11) " "Info (10041): Inferred latch for \"f\[1\]\" at jianzhong.vhd(11)" {  } { { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "f\[2\] jianzhong.vhd(11) " "Info (10041): Inferred latch for \"f\[2\]\" at jianzhong.vhd(11)" {  } { { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "y\[0\]~reg0 High " "Info: Power-up level of register \"y\[0\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 67 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "y\[0\]~reg0 data_in VCC " "Warning (14130): Reduced register \"y\[0\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 67 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "a\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"a\[0\]~4\"" {  } { { "jianzhong.vhd" "a\[0\]~4" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 33 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "c\[0\]~20 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"c\[0\]~20\"" {  } { { "jianzhong.vhd" "c\[0\]~20" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 33 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "\\x2:i\[0\]~0 10 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: \"\\x2:i\[0\]~0\"" {  } {  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:a_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:a_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 268 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_counter:a_rtl_0\|alt_counter_f10ke:wysi_counter lpm_counter:a_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:a_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"lpm_counter:a_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 432 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:a_rtl_0 " "Info: Instantiated megafunction \"lpm_counter:a_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:\\x2:i\[0\]_rtl_2 " "Info: Elaborated megafunction instantiation \"lpm_counter:\\x2:i\[0\]_rtl_2\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter lpm_counter:\\x2:i\[0\]_rtl_2 " "Info: Elaborated megafunction instantiation \"lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"lpm_counter:\\x2:i\[0\]_rtl_2\"" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 432 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:\\x2:i\[0\]_rtl_2 " "Info: Instantiated megafunction \"lpm_counter:\\x2:i\[0\]_rtl_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 10 " "Info: Parameter \"LPM_WIDTH\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "y\[0\] VCC " "Warning (13410): Pin \"y\[0\]\" stuck at VCC" {  } { { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 67 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "176 " "Info: Implemented 176 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "155 " "Info: Implemented 155 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "160 " "Info: Allocated 160 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 24 09:21:48 2009 " "Info: Processing ended: Sun May 24 09:21:48 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}