jianzhong.qsf

最基本的vhdl程序

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		jianzhong_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:25:58  MARCH 30, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name VHDL_FILE jianzhong.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_79 -to clk
set_location_assignment PIN_53 -to clr
set_location_assignment PIN_39 -to s0
set_location_assignment PIN_40 -to s1
set_location_assignment PIN_41 -to s2
set_location_assignment PIN_44 -to s3
set_location_assignment PIN_45 -to s4
set_location_assignment PIN_46 -to s5
set_location_assignment PIN_47 -to s6
set_location_assignment PIN_89 -to ds[0]
set_location_assignment PIN_90 -to ds[1]
set_location_assignment PIN_92 -to ds[2]
set_location_assignment PIN_93 -to ds[3]
set_location_assignment PIN_163 -to y[0]
set_location_assignment PIN_162 -to y[1]
set_location_assignment PIN_161 -to y[2]
set_location_assignment PIN_160 -to y[3]
set_location_assignment PIN_159 -to y[4]
set_location_assignment PIN_158 -to y[5]
set_location_assignment PIN_157 -to y[6]
set_location_assignment PIN_150 -to y[7]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 208
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 3
set_global_assignment -name FAMILY ACEX1K
set_global_assignment -name TOP_LEVEL_ENTITY jianzhong

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EP1K50QC208-3"

# -----------------------------------
# start EDA_TOOL_SETTINGS(eda_palace)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace

# end EDA_TOOL_SETTINGS(eda_palace)
# ---------------------------------