jianzhong.tan.rpt

最基本的vhdl程序

+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1K50QC208-3      ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                           ; To                                                             ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3]        ; clk        ; clk      ; None                        ; None                      ; 14.200 ns               ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[2]        ; clk        ; clk      ; None                        ; None                      ; 14.200 ns               ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1]        ; clk        ; clk      ; None                        ; None                      ; 14.200 ns               ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[0]        ; clk        ; clk      ; None                        ; None                      ; 14.200 ns               ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3]        ; clk        ; clk      ; None                        ; None                      ; 14.100 ns               ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[2]        ; clk        ; clk      ; None                        ; None                      ; 14.100 ns               ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1]        ; clk        ; clk      ; None                        ; None                      ; 14.100 ns               ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[0]        ; clk        ; clk      ; None                        ; None                      ; 14.100 ns               ;
; N/A                                     ; 67.11 MHz ( period = 14.900 ns )                    ; lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] ; d[1]                                                           ; clk        ; clk      ; None                        ; None                      ; 13.500 ns               ;
; N/A                                     ; 67.11 MHz ( period = 14.900 ns )                    ; lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] ; d[2]                                                           ; clk        ; clk      ; None                        ; None                      ; 13.500 ns               ;