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📄 t1main.src

📁 基于FPGA 的直接数字频率合成信号发生器(DDS)设计
💻 SRC
📖 第 1 页 / 共 3 页
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; .\T1main.SRC generated from: .\T1main.c

$NOMOD51

NAME	T1MAIN

P0	DATA	080H
P1	DATA	090H
P2	DATA	0A0H
P3	DATA	0B0H
AC	BIT	0D0H.6
T0	BIT	0B0H.4
T1	BIT	0B0H.5
EA	BIT	0A8H.7
T2	BIT	090H.0
IE	DATA	0A8H
P0_0	BIT	080H.0
P1_0	BIT	090H.0
P0_1	BIT	080H.1
FL	BIT	0D0H.1
P2_0	BIT	0A0H.0
P1_1	BIT	090H.1
P0_2	BIT	080H.2
P3_0	BIT	0B0H.0
P2_1	BIT	0A0H.1
P1_2	BIT	090H.2
P0_3	BIT	080H.3
P3_1	BIT	0B0H.1
P2_2	BIT	0A0H.2
P1_3	BIT	090H.3
P0_4	BIT	080H.4
P3_2	BIT	0B0H.2
P2_3	BIT	0A0H.3
P1_4	BIT	090H.4
P0_5	BIT	080H.5
EXF2	BIT	0C8H.6
RD	BIT	0B0H.7
P3_3	BIT	0B0H.3
P2_4	BIT	0A0H.4
P1_5	BIT	090H.5
P0_6	BIT	080H.6
P3_4	BIT	0B0H.4
P2_5	BIT	0A0H.5
P1_6	BIT	090H.6
P0_7	BIT	080H.7
P3_5	BIT	0B0H.5
ES	BIT	0A8H.4
P2_6	BIT	0A0H.6
P1_7	BIT	090H.7
P3_6	BIT	0B0H.6
P2_7	BIT	0A0H.7
IP	DATA	0B8H
P3_7	BIT	0B0H.7
RI	BIT	098H.0
CY	BIT	0D0H.7
INT0	BIT	0B0H.2
INT1	BIT	0B0H.3
TI	BIT	098H.1
RCAP2H	DATA	0CBH
PS	BIT	0B8H.4
SP	DATA	081H
T2EX	BIT	090H.1
OV	BIT	0D0H.2
DogLine	BIT	090H.7
RCAP2L	DATA	0CAH
C_T2	BIT	0C8H.1
WR	BIT	0B0H.6
RCLK	BIT	0C8H.5
TCLK	BIT	0C8H.4
SBUF	DATA	099H
PCON	DATA	087H
SCON	DATA	098H
TMOD	DATA	089H
TCON	DATA	088H
Line0	BIT	080H.0
Line1	BIT	080H.1
Line2	BIT	080H.2
IE0	BIT	088H.1
IE1	BIT	088H.3
B	DATA	0F0H
CP_RL2	BIT	0C8H.0
ACC	DATA	0E0H
ET0	BIT	0A8H.1
ET1	BIT	0A8H.3
TF0	BIT	088H.5
ET2	BIT	0A8H.5
TF1	BIT	088H.7
TF2	BIT	0C8H.7
RB8	BIT	098H.2
TH0	DATA	08CH
EX0	BIT	0A8H.0
IT0	BIT	088H.0
TH1	DATA	08DH
EX1	BIT	0A8H.2
TB8	BIT	098H.3
IT1	BIT	088H.2
TH2	DATA	0CDH
P	BIT	0D0H.0
SM0	BIT	098H.7
TL0	DATA	08AH
SM1	BIT	098H.6
TL1	DATA	08BH
SM2	BIT	098H.5
TL2	DATA	0CCH
PT0	BIT	0B8H.1
RS0	BIT	0D0H.3
PT1	BIT	0B8H.3
RS1	BIT	0D0H.4
PT2	BIT	0B8H.5
TR0	BIT	088H.4
TR1	BIT	088H.6
TR2	BIT	0C8H.2
PX0	BIT	0B8H.0
PX1	BIT	0B8H.2
DPH	DATA	083H
DPL	DATA	082H
EXEN2	BIT	0C8H.3
REN	BIT	098H.4
T2MOD	DATA	0C9H
T2CON	DATA	0C8H
RXD	BIT	0B0H.0
TXD	BIT	0B0H.1
F0	BIT	0D0H.5
PSW	DATA	0D0H
?PR?frefun?T1MAIN    SEGMENT CODE
?PR?ExInt0Rsp?T1MAIN SEGMENT CODE
?PR?Timer1IntRsp?T1MAIN                  SEGMENT CODE
?PR?ExInt1Rsp?T1MAIN SEGMENT CODE
?PR?Timer0IntRsp?T1MAIN                  SEGMENT CODE
?PR?SerialPortIntRsp?T1MAIN              SEGMENT CODE
?PR?Timer2IntRsp?T1MAIN                  SEGMENT CODE
?PR?FeedDog?T1MAIN   SEGMENT CODE
?PR?KeyProc?T1MAIN   SEGMENT CODE
?PR?UpdateDisplay?T1MAIN                 SEGMENT CODE
?DT?UpdateDisplay?T1MAIN                 SEGMENT DATA OVERLAYABLE
?PR?Sys_Init?T1MAIN  SEGMENT CODE
?PR?KeyScan?T1MAIN   SEGMENT CODE
?PR?main?T1MAIN      SEGMENT CODE
?DT?T1MAIN           SEGMENT DATA
?ID?T1MAIN           SEGMENT IDATA
?BI?T1MAIN           SEGMENT BIT
	EXTRN	CODE (Read7279KeyCode)
	EXTRN	CODE (_SetupFlashBit)
	EXTRN	CODE (InitialDisplayControl)
	EXTRN	CODE (_SetupHideBit)
	EXTRN	CODE (Display)
	EXTRN	CODE (GoOutAllLED)
	EXTRN	CODE (_SetupDisBuffer)
	EXTRN	DATA (?_SetupDisBuffer?BYTE)
	EXTRN	CODE (?C?LMUL)
	EXTRN	CODE (?C?ULDIV)
	EXTRN	CODE (?C?LLDIDATA)
	EXTRN	CODE (?C_STARTUP)
	PUBLIC	sta_num
	PUBLIC	i
	PUBLIC	ol
	PUBLIC	lo
	PUBLIC	Int_Num
	PUBLIC	testD1
	PUBLIC	KeyMark
	PUBLIC	freq
	PUBLIC	KeyTimer
	PUBLIC	DisStatus
	PUBLIC	BcdBuf
	PUBLIC	KeyCode
	PUBLIC	h6
	PUBLIC	Fre
	PUBLIC	h5
	PUBLIC	f6
	PUBLIC	h4
	PUBLIC	flag
	PUBLIC	f5
	PUBLIC	h3
	PUBLIC	f4
	PUBLIC	h2
	PUBLIC	f3
	PUBLIC	h1
	PUBLIC	f2
	PUBLIC	h0
	PUBLIC	f1
	PUBLIC	f0
	PUBLIC	main
	PUBLIC	KeyScan
	PUBLIC	Sys_Init
	PUBLIC	UpdateDisplay
	PUBLIC	KeyProc
	PUBLIC	FeedDog
	PUBLIC	Timer2IntRsp
	PUBLIC	SerialPortIntRsp
	PUBLIC	Timer0IntRsp
	PUBLIC	ExInt1Rsp
	PUBLIC	Timer1IntRsp
	PUBLIC	ExInt0Rsp
	PUBLIC	frefun

	RSEG  ?DT?UpdateDisplay?T1MAIN
?UpdateDisplay?BYTE:
          i?941:   DS   2

	RSEG  ?DT?T1MAIN
             f0:   DS   2
             f1:   DS   2
             h0:   DS   2
             f2:   DS   2
             h1:   DS   2
             f3:   DS   2
             h2:   DS   2
             f4:   DS   2
             h3:   DS   2
             f5:   DS   2
           flag:   DS   1
             h4:   DS   2
             f6:   DS   2
             h5:   DS   2
            Fre:   DS   32
             h6:   DS   2
       KeyTimer:   DS   1
           freq:   DS   4
         testD1:   DS   2
        Int_Num:   DS   1
             lo:   DS   1
             ol:   DS   1
              i:   DS   1
        sta_num:   DS   8

	RSEG  ?ID?T1MAIN
        KeyCode:   DS   1
         BcdBuf:   DS   5
      DisStatus:   DS   1

	RSEG  ?BI?T1MAIN
        KeyMark:   DBIT   1
; #include "AT51S_89C52.h"
; #include "hd7279.h"
; 
; #include "DisplayControl.h"
; 
; extern void KeilWordToBcd(unsigned char idata *pWord,unsigned char idata *pBcd);
; extern void KeilLongToBcd(unsigned char idata *pLong,unsigned char idata *pBcd);
; 
; //-------Use For Test-----------------------------------------------------------------------
; unsigned int testD1;
; 
; //Dog Line is for reset Watchdog chip.
; sbit	DogLine = P1^7;
; sbit	Line0 = P0^0;
; sbit	Line1 = P0^1;
; sbit	Line2 = P0^2;
; 
; 
; typedef union
; {
; 	unsigned int  Word;
; 	unsigned char Byte[2];
; 	 
; }uWordByte;
; 
; //-------------------------Use for keyboard and display----------------------------------------
; unsigned char idata KeyCode;
; unsigned char sta_num[8];
; unsigned char i;
; int  f6,f5,f4,f3,f2,f1,f0;//flash
; int  h6,h5,h4,h3,h2,h1,h0;//hide
; 
; bit       KeyMark;
; unsigned char KeyTimer;
; unsigned char idata DisStatus; 
; unsigned char idata BcdBuf[5];
; //Macro Define for DisStatus
; #define DisStatusNUMs   4
; #define Working_DS  	0
; #define TestData1_DS    1        //Use For Test
; #define TestData2_DS    2        //Use For Test
; #define Debug_DS    	3
; //Macro Define for KeyCode
; #define Status_KEYCODE  7
; #define Shift_KEYCODE   14
; #define Up_KEYCODE      21
; #define Down_KEYCODE    28
; #define Yes_KEYCODE     35
; #define Esc_KEYCODE     42
; #define Right_KEYCODE   49
; #define Left_KEYCODE    56 
; //use for interrupt
; unsigned char flag;
; unsigned char Int_Num;//溢出次数
; unsigned long freq;
; unsigned long Fre[8];
; void frefun(void);
; unsigned char ol,lo;
; 
; 
; void frefun(void)

	RSEG  ?PR?frefun?T1MAIN
frefun:
	USING	0
			; SOURCE LINE # 61
; {
			; SOURCE LINE # 62
; int i;  
;               freq=0;
			; SOURCE LINE # 64
	CLR  	A
	MOV  	freq+03H,A
	MOV  	freq+02H,A
	MOV  	freq+01H,A
	MOV  	freq,A
;                freq=(Int_Num*65536+TH1/16*4096+TH1%16*256+TL1/16*16+TL1%16)*2;
			; SOURCE LINE # 65
	MOV  	R7,Int_Num
	MOV  	R4,A
	MOV  	R5,A
	MOV  	R6,A
	MOV  	R3,A
	MOV  	R2,A
	MOV  	R1,#01H
	MOV  	R0,A
	LCALL	?C?LMUL
	MOV  	R0,AR4
	MOV  	R1,AR5
	MOV  	R2,AR6
	MOV  	R3,AR7
	MOV  	A,TH1
	SWAP 	A
	ANL  	A,#0FH
	SWAP 	A
	ANL  	A,#0F0H
	MOV  	R6,A
	CLR  	A
	MOV  	R4,A
	MOV  	R5,A
	ADD  	A,R3
	MOV  	R7,A
	MOV  	A,R2
	ADDC 	A,R6
	MOV  	R6,A
	MOV  	A,R5
	ADDC 	A,R1
	MOV  	R5,A
	MOV  	A,R4
	ADDC 	A,R0
	MOV  	R4,A
	MOV  	R0,AR4
	MOV  	R1,AR5
	MOV  	R2,AR6
	MOV  	R3,AR7
	MOV  	A,TH1
	ANL  	A,#0FH
	MOV  	R6,A
	CLR  	A
	MOV  	R4,A
	MOV  	R5,A
	ADD  	A,R3
	MOV  	R7,A
	MOV  	A,R2
	ADDC 	A,R6
	MOV  	R6,A
	MOV  	A,R5
	ADDC 	A,R1
	MOV  	R5,A
	MOV  	A,R4
	ADDC 	A,R0
	MOV  	R4,A
	MOV  	R0,AR4
	MOV  	R1,AR5
	MOV  	R2,AR6
	MOV  	R3,AR7
	MOV  	A,TL1
	SWAP 	A
	ANL  	A,#0FH
	MOV  	B,#010H
	MUL  	AB
	MOV  	R7,A
	CLR  	A
	MOV  	R4,A
	MOV  	R5,A
	MOV  	A,R3
	ADD  	A,R7
	MOV  	R3,A
	MOV  	A,R2
	ADDC 	A,B
	MOV  	R2,A
	MOV  	A,R5
	ADDC 	A,R1
	MOV  	R1,A
	MOV  	A,R4
	ADDC 	A,R0
	MOV  	R0,A
	MOV  	A,TL1
	ANL  	A,#0FH
	MOV  	R7,A
	CLR  	A
	MOV  	R6,A
	MOV  	A,R3
	ADD  	A,R7
	MOV  	R7,A
	MOV  	A,R6
	ADDC 	A,R2
	MOV  	R6,A
	MOV  	A,R5
	ADDC 	A,R1
	MOV  	R5,A
	MOV  	A,R4
	ADDC 	A,R0
	MOV  	R4,A
	CLR  	A
	MOV  	R3,#02H
	MOV  	R2,A
	MOV  	R1,A
	MOV  	R0,A
	LCALL	?C?LMUL
	MOV  	freq+03H,R7
	MOV  	freq+02H,R6
	MOV  	freq+01H,R5
	MOV  	freq,R4
; 	i = freq%10;
			; SOURCE LINE # 66
	CLR  	A
	MOV  	R3,#0AH
	MOV  	R2,A
	MOV  	R1,A
	MOV  	R0,A
	LCALL	?C?ULDIV
	MOV  	R6,AR2
	MOV  	R7,AR3
;---- Variable 'i?040' assigned to Register 'R6/R7' ----
;      	Fre[0]=i;
			; SOURCE LINE # 67
	MOV  	A,R6
	RLC  	A
	SUBB 	A,ACC
	MOV  	Fre+03H,R7
	MOV  	Fre+02H,R6
	MOV  	Fre+01H,A
	MOV  	Fre,A
; 	Fre[1]=(freq%100)/10;
			; SOURCE LINE # 68
	CLR  	A
	MOV  	R3,#064H
	MOV  	R2,A
	MOV  	R1,A
	MOV  	R0,A
	MOV  	R7,freq+03H
	MOV  	R6,freq+02H
	MOV  	R5,freq+01H
	MOV  	R4,freq
	LCALL	?C?ULDIV
	MOV  	R4,AR0
	MOV  	R5,AR1
	MOV  	R6,AR2
	MOV  	R7,AR3
	CLR  	A
	MOV  	R3,#0AH
	MOV  	R2,A
	MOV  	R1,A
	MOV  	R0,A
	LCALL	?C?ULDIV
	MOV  	Fre+07H,R7
	MOV  	Fre+06H,R6
	MOV  	Fre+05H,R5
	MOV  	Fre+04H,R4
; 	Fre[2]=(freq%1000)/100;
			; SOURCE LINE # 69
	CLR  	A
	MOV  	R3,#0E8H
	MOV  	R2,#03H
	MOV  	R1,A
	MOV  	R0,A
	MOV  	R7,freq+03H
	MOV  	R6,freq+02H
	MOV  	R5,freq+01H
	MOV  	R4,freq
	LCALL	?C?ULDIV
	MOV  	R4,AR0
	MOV  	R5,AR1
	MOV  	R6,AR2
	MOV  	R7,AR3
	CLR  	A
	MOV  	R3,#064H
	MOV  	R2,A
	MOV  	R1,A
	MOV  	R0,A
	LCALL	?C?ULDIV
	MOV  	Fre+0BH,R7
	MOV  	Fre+0AH,R6
	MOV  	Fre+09H,R5
	MOV  	Fre+08H,R4
; 	Fre[3]=(freq%10000)/1000;
			; SOURCE LINE # 70
	CLR  	A
	MOV  	R3,#010H
	MOV  	R2,#027H
	MOV  	R1,A
	MOV  	R0,A
	MOV  	R7,freq+03H
	MOV  	R6,freq+02H
	MOV  	R5,freq+01H
	MOV  	R4,freq
	LCALL	?C?ULDIV
	MOV  	R4,AR0
	MOV  	R5,AR1
	MOV  	R6,AR2
	MOV  	R7,AR3
	CLR  	A
	MOV  	R3,#0E8H
	MOV  	R2,#03H
	MOV  	R1,A
	MOV  	R0,A
	LCALL	?C?ULDIV
	MOV  	Fre+0FH,R7
	MOV  	Fre+0EH,R6
	MOV  	Fre+0DH,R5
	MOV  	Fre+0CH,R4
; 	Fre[4]=(freq%100000)/10000;
			; SOURCE LINE # 71
	MOV  	R3,#0A0H
	MOV  	R2,#086H
	MOV  	R1,#01H
	MOV  	R0,#00H
	MOV  	R7,freq+03H
	MOV  	R6,freq+02H
	MOV  	R5,freq+01H
	MOV  	R4,freq
	LCALL	?C?ULDIV
	MOV  	R4,AR0
	MOV  	R5,AR1
	MOV  	R6,AR2
	MOV  	R7,AR3
	CLR  	A
	MOV  	R3,#010H
	MOV  	R2,#027H
	MOV  	R1,A
	MOV  	R0,A
	LCALL	?C?ULDIV
	MOV  	Fre+013H,R7
	MOV  	Fre+012H,R6
	MOV  	Fre+011H,R5
	MOV  	Fre+010H,R4
; 	Fre[5]=(freq%1000000)/100000;
			; SOURCE LINE # 72
	MOV  	R3,#040H
	MOV  	R2,#042H
	MOV  	R1,#0FH
	MOV  	R0,#00H
	MOV  	R7,freq+03H
	MOV  	R6,freq+02H
	MOV  	R5,freq+01H
	MOV  	R4,freq
	LCALL	?C?ULDIV
	MOV  	R4,AR0
	MOV  	R5,AR1
	MOV  	R6,AR2
	MOV  	R7,AR3
	MOV  	R3,#0A0H
	MOV  	R2,#086H
	MOV  	R1,#01H
	MOV  	R0,#00H
	LCALL	?C?ULDIV
	MOV  	Fre+017H,R7
	MOV  	Fre+016H,R6
	MOV  	Fre+015H,R5
	MOV  	Fre+014H,R4
; 	Fre[6]=(freq%10000000)/1000000;
			; SOURCE LINE # 73

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