sw_debounce.map.qmsg

verilog键盘防抖程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 26 17:37:50 2009 " "Info: Processing started: Sun Apr 26 17:37:50 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sw_debounce -c sw_debounce " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sw_debounce -c sw_debounce" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sw_debounce.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sw_debounce.v" { { "Info" "ISGN_ENTITY_NAME" "1 sw_debounce " "Info: Found entity 1: sw_debounce" {  } { { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sw_debounce " "Info: Elaborating entity \"sw_debounce\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 43 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 50 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 50 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 50 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 50 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 23 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 29 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 23 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 29 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 23 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 29 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 23 -1 0 } } { "sw_debounce.v" "" { Text "E:/FPGA/键盘消抖/keyscanverilog/sw_debounce.v" 29 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "68 " "Info: Implemented 68 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "54 " "Info: Implemented 54 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "126 " "Info: Allocated 126 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 26 17:37:51 2009 " "Info: Processing ended: Sun Apr 26 17:37:51 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}