fir_test.mdl

Fir implementation on MATLAB and ccs

	PropName		"Components"
      }
      Name		      "Configuration"
      ExtraOptions	      "-aGenerateTraceInfo=0 -aProfileNumSamples=100 -asystemStackSize=8192 "
      CurrentDlgPage	      "Real-Time Workshop/Comments"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Arial"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      DataTypeConversion
      OutMin		      "[]"
      OutMax		      "[]"
      OutDataTypeMode	      "Inherit via back propagation"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      LockScale		      off
      ConvertRealWorld	      "Real World Value (RWV)"
      RndMeth		      "Zero"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Demux
      Outputs		      "4"
      DisplayOption	      "none"
      BusSelectionMode	      off
    }
    Block {
      BlockType		      FromWorkspace
      VariableName	      "simulink_input"
      SampleTime	      "-1"
      Interpolate	      on
      ZeroCross		      off
      OutputAfterFinalValue   "Extrapolation"
    }
    Block {
      BlockType		      Inport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      OutMin		      "[]"
      OutMax		      "[]"
      DataType		      "auto"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      SignalType	      "auto"
      SamplingMode	      "auto"
      LatchByDelayingOutsideSignal off
      LatchByCopyingInsideSignal off
      Interpolate	      on
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      OutMin		      "[]"
      OutMax		      "[]"
      DataType		      "auto"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      Scope
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
      Grid		      "on"
      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
      SaveToWorkspace	      off
      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "-1"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      "FromPortIcon"
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      TreatAsAtomicUnit	      off
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Switch
      Criteria		      "u2 >= Threshold"
      Threshold		      "0"
      InputSameDT	      on
      OutMin		      "[]"
      OutMax		      "[]"
      OutDataTypeMode	      "Inherit via internal rule"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      ZeroCross		      on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Terminator
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Arial"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    UseDisplayTextAsClickCallback off
  }
  LineDefaults {
    FontName		    "Arial"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "fir_test"
    Location		    [162, 118, 814, 628]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
    TiledPageScale	    1
    ShowPageBoundaries	    off
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      "Aanalog to Digital \nConverter"
      Ports		      [0, 1]
      Position		      [60, 200, 150, 260]
      BackgroundColor	      "lightBlue"
      SourceBlock	      "c6416dsklib/ADC"
      SourceType	      "C6416DSK ADC"
      ADCsource		      "Line In"
      MicGain		      off
      Stereo		      off
      SampleRate	      "8 kHz"
      CodecDataFormat	      "16-bit"
      OutputDataType	      "Integer"
      Scaling		      "Normalize"
      SourceGain	      " 0.0"
      FrameSize		      "1"
      inheritSampleTime	      off
    }
    Block {
      BlockType		      Reference
      Name		      "C6416DSK"
      Tag		      "ccslinktgtpref"
      Ports		      []
      Position		      [60, 25, 126, 70]
      UserDataPersistent      on
      UserData		      "DataTag0"
      SourceBlock	      "etargetslib/Target Preferences\nTemplate"
      SourceType	      "Target Preferences"
      ShowPortLabels	      "FromPortIcon"
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
    }
    Block {
      BlockType		      Reference
      Name		      "Digital to Analog \nConverter"
      Ports		      [1]
      Position		      [455, 161, 555, 229]
      BackgroundColor	      "lightBlue"
      SourceBlock	      "c6416dsklib/DAC"
      SourceType	      "C6416DSK DAC"
      CodecDataFormat	      "16-bit"
      SampleRate	      "8 kHz"
      Scaling		      "Normalize"
      DacAtten		      " 0.0"
      OverflowMode	      "Wrap"
    }
    Block {
      BlockType		      SubSystem
      Name		      "FILTER"
      Ports		      [2, 1]
      Position		      [220, 158, 390, 227]
      BackgroundColor	      "green"
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"