📄 mealy.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 2/ 96( 2%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdlexperiments\maxplus\experiment7\mealy.rpt
mealy
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 clk
Device-Specific Information: d:\vhdlexperiments\maxplus\experiment7\mealy.rpt
mealy
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 3 reset
Device-Specific Information: d:\vhdlexperiments\maxplus\experiment7\mealy.rpt
mealy
** EQUATIONS **
clk : INPUT;
datain : INPUT;
reset : INPUT;
-- Node name is ':11' = 'current_state0'
-- Equation name is 'current_state0', location is LC4_C9, type is buried.
current_state0 = DFFE( _LC8_C7, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
-- Node name is ':10' = 'current_state1'
-- Equation name is 'current_state1', location is LC3_C7, type is buried.
current_state1 = DFFE( _LC6_C7, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
-- Node name is ':9' = 'current_state2'
-- Equation name is 'current_state2', location is LC1_C7, type is buried.
current_state2 = DFFE( _LC5_C7, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC5_C9;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC7_C9;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC1_C9;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC2_C9;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _LC3_C9;
-- Node name is ':736'
-- Equation name is '_LC4_C7', type is buried
_LC4_C7 = LCELL( _EQ001);
_EQ001 = current_state0 & current_state1 & !current_state2;
-- Node name is ':746'
-- Equation name is '_LC7_C7', type is buried
_LC7_C7 = LCELL( _EQ002);
_EQ002 = !current_state0 & current_state1 & !current_state2;
-- Node name is ':766'
-- Equation name is '_LC2_C7', type is buried
_LC2_C7 = LCELL( _EQ003);
_EQ003 = !current_state0 & !current_state1 & !current_state2;
-- Node name is ':769'
-- Equation name is '_LC5_C7', type is buried
_LC5_C7 = LCELL( _EQ004);
_EQ004 = !datain & _LC2_C7 & _LC5_C7
# !datain & _LC4_C7;
-- Node name is ':781'
-- Equation name is '_LC6_C9', type is buried
_LC6_C9 = LCELL( _EQ005);
_EQ005 = !current_state0 & current_state1 & !current_state2 & datain
# current_state0 & !current_state1 & !current_state2 & !datain;
-- Node name is ':784'
-- Equation name is '_LC6_C7', type is buried
_LC6_C7 = LCELL( _EQ006);
_EQ006 = !datain & _LC2_C7 & _LC6_C7
# !_LC2_C7 & _LC6_C9;
-- Node name is ':799'
-- Equation name is '_LC8_C7', type is buried
_LC8_C7 = LCELL( _EQ007);
_EQ007 = datain & _LC2_C7
# _LC2_C7 & _LC8_C7
# datain & _LC7_C7;
-- Node name is ':814'
-- Equation name is '_LC3_C9', type is buried
_LC3_C9 = LCELL( _EQ008);
_EQ008 = current_state2 & datain
# !current_state0 & datain
# !current_state1 & datain
# current_state1 & !current_state2 & !datain
# !current_state0 & current_state1 & !current_state2
# current_state0 & !current_state1 & !current_state2;
-- Node name is ':829'
-- Equation name is '_LC2_C9', type is buried
_LC2_C9 = LCELL( _EQ009);
_EQ009 = !current_state0 & !current_state1 & !datain
# current_state2
# current_state0 & current_state1;
-- Node name is ':844'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = LCELL( _EQ010);
_EQ010 = !current_state0 & current_state1 & datain
# current_state2
# current_state0 & !current_state1;
-- Node name is ':859'
-- Equation name is '_LC7_C9', type is buried
_LC7_C9 = LCELL( _EQ011);
_EQ011 = current_state1 & !current_state2 & !datain
# !current_state0 & !current_state2 & !datain;
-- Node name is ':874'
-- Equation name is '_LC5_C9', type is buried
_LC5_C9 = LCELL( _EQ012);
_EQ012 = current_state2
# current_state1
# current_state0 & !datain;
Project Information d:\vhdlexperiments\maxplus\experiment7\mealy.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,364K
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