counter60.vhd

来自「计数器、频率计、优先编码器、数码管扫描电路、数据选择器」· VHDL 代码 · 共 46 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter60 IS
	PORT(
		clk,clr		: IN	STD_LOGIC;
		y0,y1		: buffer	STD_LOGIC_VECTOR(3 downto 0);
		oc			: OUT	STD_LOGIC);
END counter60;
ARCHITECTURE a OF counter60 IS
signal q:std_logic;
		BEGIN
	p1: Process(clk)
     	Begin
		if(rising_edge(clk)) then
			if (clr='1') then
				y0<=(others=>'0');q<='0';
			else 
				y0<=y0+1;q<='1';
			if y0=9 then
				y0<=(others=>'0');q<='0';
			end if;
			end if;
		end if;
	end process p1;

    p2: Process(q)
		Begin
		if(rising_edge(q)) then
			if(clr='1') then
				y1<=(others=>'0'); 
			 else
				 y1<=y1+1; 
			 if y1=5 then
				y1<=(others=>'0'); 
			end if;
			end if;
		end if;
	end process p2;
oc<='1'when y0="1001" and y1="0101"
		else '0';
END a;