📄 scan_led.rpt
字号:
11 - - - 01 OUTPUT 0 0 0 0 BT1
64 - - B -- OUTPUT 0 0 0 0 BT2
28 - - C -- OUTPUT 0 0 0 0 BT3
5 - - - 05 OUTPUT 0 0 0 0 BT4
6 - - - 04 OUTPUT 0 0 0 0 BT5
70 - - A -- OUTPUT 0 0 0 0 BT6
39 - - - 11 OUTPUT 0 0 0 0 BT7
79 - - - 24 OUTPUT 0 0 0 0 SG0
23 - - B -- OUTPUT 0 0 0 0 SG1
72 - - A -- OUTPUT 0 0 0 0 SG2
19 - - A -- OUTPUT 0 0 0 0 SG3
65 - - B -- OUTPUT 0 0 0 0 SG4
73 - - A -- OUTPUT 0 0 0 0 SG5
17 - - A -- OUTPUT 0 0 0 0 SG6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\vhdlexperiments\maxplus\1\scan_led.rpt
scan_led
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdlexperiments\maxplus\1\scan_led.rpt
scan_led
** EQUATIONS **
-- Node name is 'BT0'
-- Equation name is 'BT0', type is output
BT0 = VCC;
-- Node name is 'BT1'
-- Equation name is 'BT1', type is output
BT1 = GND;
-- Node name is 'BT2'
-- Equation name is 'BT2', type is output
BT2 = GND;
-- Node name is 'BT3'
-- Equation name is 'BT3', type is output
BT3 = GND;
-- Node name is 'BT4'
-- Equation name is 'BT4', type is output
BT4 = GND;
-- Node name is 'BT5'
-- Equation name is 'BT5', type is output
BT5 = GND;
-- Node name is 'BT6'
-- Equation name is 'BT6', type is output
BT6 = GND;
-- Node name is 'BT7'
-- Equation name is 'BT7', type is output
BT7 = GND;
-- Node name is 'SG0'
-- Equation name is 'SG0', type is output
SG0 = GND;
-- Node name is 'SG1'
-- Equation name is 'SG1', type is output
SG1 = VCC;
-- Node name is 'SG2'
-- Equation name is 'SG2', type is output
SG2 = VCC;
-- Node name is 'SG3'
-- Equation name is 'SG3', type is output
SG3 = GND;
-- Node name is 'SG4'
-- Equation name is 'SG4', type is output
SG4 = GND;
-- Node name is 'SG5'
-- Equation name is 'SG5', type is output
SG5 = GND;
-- Node name is 'SG6'
-- Equation name is 'SG6', type is output
SG6 = GND;
Project Information d:\vhdlexperiments\maxplus\1\scan_led.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,125K
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