scan_led.vhd

计数器、频率计、优先编码器、数码管扫描电路、数据选择器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity scan_led is
	port(
			CLK	: IN 	std_logic;
			SG	: out 	std_logic_vector(6 downto 0);
			BT	: out 	std_logic_vector(7 downto 0));
end scan_led;

architecture a of scan_led is 
	signal cnt8	: std_logic_vector(2 downto 0);
	signal 	A	: integer range 0 to 15;
begin

p1:process(cnt8)
	begin
		case cnt8 is 
			when "000" => BT<="00000001"; A<=1;
			when "001" => BT<="00000010"; A<=3;
			when "010" => BT<="00000100"; A<=5;
			when "011" => BT<="00001000"; A<=7;
			when "100" => BT<="00010000"; A<=9;
			when "101" => BT<="00100000"; A<=11;
			when "110" => BT<="01000000"; A<=13;
			when "111" => BT<="10000000"; A<=15;
			when others => null;
		end case;
end process p1;

p2:process(clk)
  begin 
	if clk'event and clk='1' then
		if cnt8<="111" then cnt8<="000";
			else
				cnt8<=cnt8+1;
		end if;
	end if;
end process p2;
p3:process(A)
begin
 	case A is  
		when 0  => SG <= "0111111";---0 
		when 1  => SG <= "0000110";---1 
		when 2  => SG <= "1011011";---2 
		when 3  => SG <= "1001111";---3
		when 4  => SG <= "1100110";---4 
		when 5  => SG <= "1101101";---5 
		when 6  => SG <= "1111101";---6
		when 7  => SG <= "0000111";---7
		when 8  => SG <= "1111111";---8 
		when 9  => SG <= "1100111";---9
		when 10 => SG <= "1110111";---a	
		when 11 => SG <= "0011111";---b
		when 12 => SG <= "0111001";---c
		when 13 => SG <= "0111101";---d
		when 14 => SG <= "1111001";---e
		when 15 => SG <= "1000111";---f
		when others => null;
   end case;
  end process p3;
end a;