乒乓球游戏机。.txt

设计一个乒乓球游戏机

 CORNA的VHDL程序
   library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity corna is
   port(clr,af,aj,bf,bj,clk:in std_logic;
        shift:out std_logic_vector(7 downto 0);
        ah,al,bh,bl:out std_logic_vector(3 downto 0));
end corna;
architecture corn_arc of corna is
signal amark,bmark:integer;
begin
  process (clr,clk)
  variable a,b:std_logic;
  variable she:std_logic_vector(7 downto 0);
  begin
    if clr='0' then
       a:='0';
       b:='0';
       she:="00000000";
       amark<=0;
       bmark<=0;
     elsif clk'event and clk='1' then
        if a='0' and b='0' and af='0' then               
           a:='1';
           she:="10000000";
      elsif a='0' and b='0' and bf='0' then                   
          b:='1';
           she:="00000001";
      elsif a='1' and b='0' then                    
         if she>8 then
            if bj='0' then
               amark<=amark+1;
                a:='0';
                b:='0';
                she:="00000000";
             else
               she:='0' & she(7 downto 1);
             end if; 
         elsif she=0 then
               amark<=amark+1;
                a:='0';
                b:='0';
             else
               if bj='0' then
                 a:='0';
                b:='1';
               else
               she:='0' & she(7 downto 1);
             end if; 
           end if;
elsif a='0' and b='1' then
if she<16 and she/=0 then
if aj='0' then
bmark<=bmark+1;
a:='0';
b:='0';
she:="00000000";
else
she:=she(6 downto 0) & '0';
end if;
elsif she=0 then
bmark<=bmark+1;
a:='0';
b:='0';
else
if aj='0' then
a:='1';
b:='0';
else
she:=she(6 downto 0) & '0';
end if;
end if;
end if;
end if;
shift<=she;
end process;

process(clk,clr,amark,bmark)
variable aha,ala,bha,bla:std_logic_vector(3 downto 0);
variable tmp1,tmp2:integer;
begin
if clr='0' then
aha:="0000";
ala:="0000";
bha:="0000";
bla:="0000";
tmp1:=0;
tmp2:=0;
elsif clk'event and clk='1' then
if amark>tmp1 then
if ala="1001"then
ala:="0000";
aha:=aha+1;
tmp1:=tmp1+1;
else
ala:=ala+1;
tmp1:=tmp1+1;
end if;
end if;
if bmark>tmp2 then
if bla="1001"then
bla:="0000";
bha:=bha+1;
tmp2:=tmp2+1;
else
bla:=bla+1;
tmp2:=tmp2+1;
end if;
end if;
end if;
al<=ala;
bl<=bla;
ah<=aha;
bh<=bha;
end process;
end corn_arc;

CH41A的VHDL程序
library ieee;
use ieee.std_logic_1164.all;
entity ch41a is
port(sel:in std_logic_vector(2 downto 0);
d0,d1,d2,d3:in std_logic_vector(3 downto 0);
q:out std_logic_vector(3 downto 0));
end ch41a;
architecture ch41_arc of ch41a is
begin
process(sel)
begin
case sel is
when"100"=>q<=d0;
when"101"=>q<=d1;
when"000"=>q<=d2;
when others=>q<=d3;
end case;
end process;
end ch41_arc;

SEL的VHDL程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sel is
port(clk:in std_logic;
sell:out std_logic_vector(2 downto 0));
end sel;
architecture sel_arc of sel is
begin
process(clk)
variable tmp:std_logic_vector(2 downto 0);
begin
if clk'event and clk='1' then
if tmp="000"then
tmp:="001";
elsif tmp="001"then
tmp:="100";
elsif tmp="100"then
tmp:="101";
elsif tmp="101"then
tmp:="000";
end if;
end if;
sell<=tmp;
end process;
end sel_arc;

DISP的VHDL程序
library ieee;
use ieee.std_logic_1164.all;
entity disp is
port(d:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0));
end disp;
architecture disp_arc of disp is
begin
process(d)
begin
case d is
when"0000"=>q<="0111111";
when"0001"=>q<="0000110";
when"0010"=>q<="1011011";
when"0011"=>q<="1001111";
when"0100"=>q<="1100110";
when"0101"=>q<="1101101";
when"0110"=>q<="1111101";
when"0111"=>q<="0100111";
when"1000"=>q<="1111111";
when others=>q<="1101111";
end case;
end process;
end disp_arc;