stopwatch.map.rpt

利用Quarteus II 6.0 设计一个秒表

;     -- synchronous clear/load mode          ; 2     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 25    ;
; I/O pins                                    ; 19    ;
; Maximum fan-out node                        ; start ;
; Maximum fan-out                             ; 28    ;
; Total fan-out                               ; 351   ;
; Average fan-out                             ; 3.22  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |stopwatch                 ; 90 (90)     ; 25           ; 0           ; 0    ; 19   ; 0            ; 65 (65)      ; 1 (1)             ; 24 (24)          ; 0 (0)           ; 0 (0)      ; |stopwatch          ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; sg[0]$latch                                        ; Mux19               ; yes                    ;
; sg[1]$latch                                        ; Mux19               ; yes                    ;
; sg[2]$latch                                        ; Mux19               ; yes                    ;
; sg[3]$latch                                        ; Mux19               ; yes                    ;
; sg[4]$latch                                        ; Mux19               ; yes                    ;
; sg[5]$latch                                        ; Mux19               ; yes                    ;
; sg[6]$latch                                        ; Mux19               ; yes                    ;
; Number of user-specified and inferred latches = 7  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 25    ;
; Number of registers using Synchronous Clear  ; 2     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 22    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |stopwatch|count1[1]       ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |stopwatch|count2[1]       ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |stopwatch|count3[1]       ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |stopwatch|count5[1]       ;
; 5:1                ; 3 bits    ; 9 LEs         ; 3 LEs                ; 6 LEs                  ; Yes        ; |stopwatch|count4[1]       ;
; 5:1                ; 3 bits    ; 9 LEs         ; 3 LEs                ; 6 LEs                  ; Yes        ; |stopwatch|count6[2]       ;
; 8:1                ; 3 bits    ; 15 LEs        ; 12 LEs               ; 3 LEs                  ; No         ; |stopwatch|Mux11           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-----------------------------------------------------+
; Source assignments for Top-level Entity: |stopwatch ;
+----------------+-------+------+---------------------+
; Assignment     ; Value ; From ; To                  ;
+----------------+-------+------+---------------------+
; POWER_UP_LEVEL ; Low   ; -    ; count6[0]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count6[1]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count6[2]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count5[0]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count5[1]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count5[2]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count5[3]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count4[0]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count4[1]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count4[2]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count3[0]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count3[1]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count3[2]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count3[3]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count2[0]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count2[1]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count2[2]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count2[3]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count1[0]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count1[1]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count1[2]           ;
; POWER_UP_LEVEL ; Low   ; -    ; count1[3]           ;
+----------------+-------+------+---------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun May 17 00:59:14 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off stopwatch -c stopwatch
Info: Found 2 design units, including 1 entities, in source file stopwatch.vhd
    Info: Found design unit 1: stopwatch-disp_8_led
    Info: Found entity 1: stopwatch
Info: Elaborating entity "stopwatch" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(34): signal "count6" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(35): signal "count5" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(37): signal "count4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(38): signal "count3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(40): signal "count2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(41): signal "count1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at stopwatch.vhd(115): inferring latch(es) for signal or variable "sg", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at stopwatch.vhd(115): inferred latch for "sg[0]"
Info (10041): Verilog HDL or VHDL info at stopwatch.vhd(115): inferred latch for "sg[1]"
Info (10041): Verilog HDL or VHDL info at stopwatch.vhd(115): inferred latch for "sg[2]"
Info (10041): Verilog HDL or VHDL info at stopwatch.vhd(115): inferred latch for "sg[3]"
Info (10041): Verilog HDL or VHDL info at stopwatch.vhd(115): inferred latch for "sg[4]"
Info (10041): Verilog HDL or VHDL info at stopwatch.vhd(115): inferred latch for "sg[5]"
Info (10041): Verilog HDL or VHDL info at stopwatch.vhd(115): inferred latch for "sg[6]"
Warning: Latch sg[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cnt8[2]
Warning: Latch sg[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cnt8[2]
Warning: Latch sg[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal count4[0]
Warning: Latch sg[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cnt8[2]
Warning: Latch sg[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cnt8[2]
Warning: Latch sg[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cnt8[2]
Warning: Latch sg[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cnt8[2]
Info: Implemented 109 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 15 output pins
    Info: Implemented 90 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings
    Info: Processing ended: Sun May 17 00:59:16 2009
    Info: Elapsed time: 00:00:03