📄 stopwatch.tan.rpt
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; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_led ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_led' ;
+-------+------------------------------------------------+---------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cnt8[1] ; cnt8[1] ; clk_led ; clk_led ; None ; None ; 2.993 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cnt8[0] ; cnt8[1] ; clk_led ; clk_led ; None ; None ; 2.806 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cnt8[1] ; cnt8[2] ; clk_led ; clk_led ; None ; None ; 1.915 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[2] ; sg[4]$latch ; clk_led ; clk_led ; None ; None ; 8.286 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[2] ; sg[6]$latch ; clk_led ; clk_led ; None ; None ; 8.208 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[2] ; sg[2]$latch ; clk_led ; clk_led ; None ; None ; 7.922 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cnt8[2] ; cnt8[2] ; clk_led ; clk_led ; None ; None ; 1.053 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cnt8[0] ; cnt8[2] ; clk_led ; clk_led ; None ; None ; 0.906 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cnt8[0] ; cnt8[0] ; clk_led ; clk_led ; None ; None ; 0.898 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[2] ; sg[5]$latch ; clk_led ; clk_led ; None ; None ; 7.490 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[1] ; sg[4]$latch ; clk_led ; clk_led ; None ; None ; 7.410 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[2] ; sg[0]$latch ; clk_led ; clk_led ; None ; None ; 7.254 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[0] ; sg[4]$latch ; clk_led ; clk_led ; None ; None ; 7.223 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[2] ; sg[1]$latch ; clk_led ; clk_led ; None ; None ; 7.222 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[2] ; sg[3]$latch ; clk_led ; clk_led ; None ; None ; 7.119 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[1] ; sg[6]$latch ; clk_led ; clk_led ; None ; None ; 6.881 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[0] ; sg[6]$latch ; clk_led ; clk_led ; None ; None ; 6.684 ns ;
; N/A ; Restricted to 387.15 MHz ( period = 2.583 ns ) ; cnt8[1] ; sg[0]$latch ; clk_led ; clk_led ; None ; None ; 6.354 ns ;
+-------+------------------------------------------------+---------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-----------------------------------------+-----------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 178.51 MHz ( period = 5.602 ns ) ; count1[3] ; count2[0] ; clk ; clk ; None ; None ; 5.355 ns ;
; N/A ; 183.39 MHz ( period = 5.453 ns ) ; count1[0] ; count2[0] ; clk ; clk ; None ; None ; 5.206 ns ;
; N/A ; 188.68 MHz ( period = 5.300 ns ) ; count1[1] ; count2[0] ; clk ; clk ; None ; None ; 5.053 ns ;
; N/A ; 194.40 MHz ( period = 5.144 ns ) ; count2[3] ; count5[0] ; clk ; clk ; None ; None ; 4.895 ns ;
; N/A ; 194.40 MHz ( period = 5.144 ns ) ; count2[3] ; count5[1] ; clk ; clk ; None ; None ; 4.895 ns ;
; N/A ; 194.40 MHz ( period = 5.144 ns ) ; count2[3] ; count5[2] ; clk ; clk ; None ; None ; 4.895 ns ;
; N/A ; 195.66 MHz ( period = 5.111 ns ) ; count1[2] ; count2[0] ; clk ; clk ; None ; None ; 4.864 ns ;
; N/A ; 196.70 MHz ( period = 5.084 ns ) ; count1[3] ; count5[0] ; clk ; clk ; None ; None ; 4.837 ns ;
; N/A ; 196.70 MHz ( period = 5.084 ns ) ; count1[3] ; count5[1] ; clk ; clk ; None ; None ; 4.837 ns ;
; N/A ; 196.70 MHz ( period = 5.084 ns ) ; count1[3] ; count5[2] ; clk ; clk ; None ; None ; 4.837 ns ;
; N/A ; 198.18 MHz ( period = 5.046 ns ) ; count4[1] ; count5[0] ; clk ; clk ; None ; None ; 4.799 ns ;
; N/A ; 198.18 MHz ( period = 5.046 ns ) ; count4[1] ; count5[1] ; clk ; clk ; None ; None ; 4.799 ns ;
; N/A ; 198.18 MHz ( period = 5.046 ns ) ; count4[1] ; count5[2] ; clk ; clk ; None ; None ; 4.799 ns ;
; N/A ; 201.98 MHz ( period = 4.951 ns ) ; count2[3] ; count4[0] ; clk ; clk ; None ; None ; 4.688 ns ;
; N/A ; 201.98 MHz ( period = 4.951 ns ) ; count2[3] ; count4[1] ; clk ; clk ; None ; None ; 4.688 ns ;
; N/A ; 201.98 MHz ( period = 4.951 ns ) ; count2[3] ; count4[2] ; clk ; clk ; None ; None ; 4.688 ns ;
; N/A ; 202.63 MHz ( period = 4.935 ns ) ; count1[0] ; count5[0] ; clk ; clk ; None ; None ; 4.688 ns ;
; N/A ; 202.63 MHz ( period = 4.935 ns ) ; count1[0] ; count5[1] ; clk ; clk ; None ; None ; 4.688 ns ;
; N/A ; 202.63 MHz ( period = 4.935 ns ) ; count1[0] ; count5[2] ; clk ; clk ; None ; None ; 4.688 ns ;
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