stopwatch.txt

利用Quarteus II 6.0 设计一个秒表

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;
entity stopwatch is
  port (clk  : in  std_logic;
        clk_led : in std_logic;------------------------
        start: in  bit;--秒表计数的开始
        stop : in  bit;--秒表计数的停止
        sg   : out std_logic_vector(6 downto 0);
        bt   : out std_logic_vector(7 downto 0));
end entity stopwatch;
architecture disp_8_led of stopwatch is 
signal cnt8:std_logic_vector(2 downto 0);
signal a :integer range 0 to 15;
signal count1 : integer range 0 to 9:=0;
signal count2 : integer range 0 to 9:=0;
signal count3 : integer range 0 to 9:=0;
signal count4 : integer range 0 to 5:=0;
signal count5 : integer range 0 to 9:=0;
signal count6 : integer range 0 to 5:=0;
begin
p1:process(cnt8)
begin
case cnt8  is
when "000"=>bt<="11111110";a<=count6;
when "001"=>bt<="11111101";a<=count5;
when "010"=>bt<="11111011";a<=10;
when "011"=>bt<="11110111";a<=count4;
when "100"=>bt<="11101111";a<=count3;
when "101"=>bt<="11011111";a<=10;
when "110"=>bt<="10111111";a<=count2;
when "111"=>bt<="01111111";a<=count1;
when others=>null;
end case;
end process p1;
p2:process(clk)
begin
if clk'event and clk ='1' then 
   if start='0' then
      count1<=0;
      count2<=0;
      count3<=0;
      count4<=0;
      count5<=0;
      count6<=0;
   elsif stop='1' then
   if count1=9 then count1<=0; 
      if count2=9 then count2<=0;
         if count3=9 then count3<=0;
            if count4=5 then count4<=0;
               if count5=9 then count5<=0;
                   if count6=5 then count6<=0;
                    else count6<=count6+1;end if;
               else count5<=count5+1;end if;
            else count4<=count4+1;end if;
         else count3<=count3+1;end if;
      else count2<=count2+1;end if;
   else count1<=count1+1;end if;
end if;
end if;
end process p2;
process(clk_led)
begin
if rising_edge(clk_led) then
   cnt8<=cnt8+1;
end if;
end process;
p3:process(a)
begin
case a is
when 0=>sg<="0111111";when 1=>sg<="0000110";
when 2=>sg<="1011011";when 3=>sg<="1001111";
when 4=>sg<="1100110";when 5=>sg<="1101101";
when 6=>sg<="1111101";when 7=>sg<="0000111";
when 8=>sg<="1111111";when 9=>sg<="1101111";
when 10=>sg<="1000000";--when 11=>sg<="1111100";
--when 12=>sg<="0111001";when 13=>sg<="1011110";
--when 14=>sg<="1111001";when 15=>sg<="1110001";
when others =>null;
  end case;
end process p3;
end architecture disp_8_led;