wopt.gfl

波束成型

# XST (Creating Lso File) : 
eexy.lso
# xst flow : RunXST
eexy_summary.html
# xst flow : RunXST
eexy.syr
eexy.prj
eexy.sprj
eexy.ana
eexy.stx
eexy.cmd_log
# XST (Creating Lso File) : 
eexy.lso
# xst flow : RunXST
eexy_summary.html
# xst flow : RunXST
eexy.syr
eexy.prj
eexy.sprj
eexy.ana
eexy.stx
eexy.cmd_log
# XST (Creating Lso File) : 
eexy.lso
# xst flow : RunXST
eexy_summary.html
# xst flow : RunXST
eexy.syr
eexy.prj
eexy.sprj
eexy.ana
eexy.stx
eexy.cmd_log
eexy.ngc
eexy.ngr
# Bencher : Creating project file
eexywave_bencher.prj
# ProjNav -> New Source -> TBW
eexywave.vhw
eexywave.ano
eexywave.tfw
eexywave.ant
# Bencher : Creating project file
eexywave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
eexywave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
eexywave_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
eexywave.vhw
eexywave.ano
eexywave.tfw
eexywave.ant
# ModelSim : Simulate Behavioral Verilog Model
eexywave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
eexywave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher : Creating project file
eexywave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
muxe.lso
# xst flow : RunXST
muxe_summary.html
# xst flow : RunXST
muxe.syr
muxe.prj
muxe.sprj
muxe.ana
muxe.stx
muxe.cmd_log
# XST (Creating Lso File) : 
muxe.lso
# xst flow : RunXST
muxe_summary.html
# xst flow : RunXST
muxe.syr
muxe.prj
muxe.sprj
muxe.ana
muxe.stx
muxe.cmd_log
# XST (Creating Lso File) : 
muxe.lso
# xst flow : RunXST
muxe_summary.html
# xst flow : RunXST
muxe.syr
muxe.prj
muxe.sprj
muxe.ana
muxe.stx
muxe.cmd_log
# XST (Creating Lso File) : 
muxe.lso
# xst flow : RunXST
muxe_summary.html
# xst flow : RunXST
muxe.syr
muxe.prj
muxe.sprj
muxe.ana
muxe.stx
muxe.cmd_log
muxe.ngc
muxe.ngr
# Bencher : Creating project file
muxewave_bencher.prj
# ProjNav -> New Source -> TBW
muxewave.vhw
muxewave.ano
muxewave.tfw
muxewave.ant
# Bencher : Creating project file
muxewave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
muxewave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
muxewave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher : Creating project file
muxewave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
gw.lso
# xst flow : RunXST
gw_summary.html
# xst flow : RunXST
gw.syr
gw.prj
gw.sprj
gw.ana
gw.stx
gw.cmd_log
eexy.ngc
muxe.ngc
eexy.ngr
muxe.ngr
# XST (Creating Lso File) : 
gw.lso
# xst flow : RunXST
gw_summary.html
# xst flow : RunXST
gw.syr
gw.prj
gw.sprj
gw.ana
gw.stx
gw.cmd_log
eexy.ngc
muxe.ngc
gw.ngc
eexy.ngr
muxe.ngr
gw.ngr
# Bencher : Creating project file
gwwave_bencher.prj
# ProjNav -> New Source -> TBW
gwwave.vhw
gwwave.ano
gwwave.tfw
gwwave.ant
# Bencher : Creating project file
gwwave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
gwwave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
gwwave.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher : Creating project file
gwwave_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# xst flow : RunXST
gw_summary.html