_primary.vhd

来自「波束成型」· VHDL 代码 · 共 43 行

library verilog;
use verilog.vl_types.all;
entity muxe is
    port(
        mux2            : in     vl_logic_vector(15 downto 0);
        a0r             : in     vl_logic_vector(15 downto 0);
        a0i             : in     vl_logic_vector(15 downto 0);
        a1r             : in     vl_logic_vector(15 downto 0);
        a1i             : in     vl_logic_vector(15 downto 0);
        a2r             : in     vl_logic_vector(15 downto 0);
        a2i             : in     vl_logic_vector(15 downto 0);
        a3r             : in     vl_logic_vector(15 downto 0);
        a3i             : in     vl_logic_vector(15 downto 0);
        a4r             : in     vl_logic_vector(15 downto 0);
        a4i             : in     vl_logic_vector(15 downto 0);
        a5r             : in     vl_logic_vector(15 downto 0);
        a5i             : in     vl_logic_vector(15 downto 0);
        a6r             : in     vl_logic_vector(15 downto 0);
        a6i             : in     vl_logic_vector(15 downto 0);
        a7r             : in     vl_logic_vector(15 downto 0);
        a7i             : in     vl_logic_vector(15 downto 0);
        q0r             : out    vl_logic_vector(15 downto 0);
        q0i             : out    vl_logic_vector(15 downto 0);
        q1r             : out    vl_logic_vector(15 downto 0);
        q1i             : out    vl_logic_vector(15 downto 0);
        q2r             : out    vl_logic_vector(15 downto 0);
        q2i             : out    vl_logic_vector(15 downto 0);
        q3r             : out    vl_logic_vector(15 downto 0);
        q3i             : out    vl_logic_vector(15 downto 0);
        q4r             : out    vl_logic_vector(15 downto 0);
        q4i             : out    vl_logic_vector(15 downto 0);
        q5r             : out    vl_logic_vector(15 downto 0);
        q5i             : out    vl_logic_vector(15 downto 0);
        q6r             : out    vl_logic_vector(15 downto 0);
        q6i             : out    vl_logic_vector(15 downto 0);
        q7r             : out    vl_logic_vector(15 downto 0);
        q7i             : out    vl_logic_vector(15 downto 0);
        clk             : in     vl_logic;
        start           : in     vl_logic;
        rdy             : out    vl_logic
    );
end muxe;