_primary.vhd

来自「波束成型」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity gee is
    port(
        der             : in     vl_logic_vector(15 downto 0);
        dei             : in     vl_logic_vector(15 downto 0);
        ykr             : in     vl_logic_vector(15 downto 0);
        yki             : in     vl_logic_vector(15 downto 0);
        eer             : out    vl_logic_vector(15 downto 0);
        eei             : out    vl_logic_vector(15 downto 0);
        clk             : in     vl_logic;
        start           : in     vl_logic;
        rdy             : out    vl_logic
    );
end gee;