prev_cmp_divide.map.qmsg

用VHDL开发的数字钟资料 完整的实验代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 22 19:32:52 2009 " "Info: Processing started: Wed Apr 22 19:32:52 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off divide -c divide " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off divide -c divide" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WSGN_MEGAFN_REPLACE" "divide G:/edatest/yulin/yulin/clock/divide/divide.vhd " "Warning: Entity \"divide\" obtained from \"G:/edatest/yulin/yulin/clock/divide/divide.vhd\" instead of from Quartus II megafunction library" {  } {  } 0 0 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus II megafunction library" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divide.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file divide.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide-one " "Info: Found design unit 1: divide-one" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 divide " "Info: Found entity 1: divide" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "divide " "Info: Elaborating entity \"divide\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "c1\[0\]~0 20 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=20) from the following logic: \"c1\[0\]~0\"" {  } { { "divide.vhd" "c1\[0\]~0" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 18 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:c1_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:c1_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:c1_rtl_0 " "Info: Instantiated megafunction \"lpm_counter:c1_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 20 " "Info: Parameter \"LPM_WIDTH\" = \"20\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_counter:c1_rtl_0\|alt_counter_f10ke:wysi_counter lpm_counter:c1_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:c1_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"lpm_counter:c1_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 425 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Info: Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "38 " "Info: Implemented 38 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "177 " "Info: Peak virtual memory: 177 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 22 19:32:59 2009 " "Info: Processing ended: Wed Apr 22 19:32:59 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}