prev_cmp_divide.tan.qmsg

来自「用VHDL开发的数字钟资料 完整的实验代码」· QMSG 代码 · 共 12 行 · 第 1/2 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 8 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:c1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] register out1 52.08 MHz 19.2 ns Internal " "Info: Clock \"clk\" has Internal fmax of 52.08 MHz between source register \"lpm_counter:c1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]\" and destination register \"out1\" (period= 19.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.600 ns + Longest register register " "Info: + Longest register to register delay is 15.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:c1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 1 REG LC2_C17 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C17; Fanout = 5; REG Node = 'lpm_counter:c1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 4.600 ns LessThan2~336 2 COMB LC1_C13 1 " "Info: 2: + IC(2.300 ns) + CELL(2.300 ns) = 4.600 ns; Loc. = LC1_C13; Fanout = 1; COMB Node = 'LessThan2~336'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] LessThan2~336 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 7.500 ns LessThan2~339 3 COMB LC5_C13 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 7.500 ns; Loc. = LC5_C13; Fanout = 1; COMB Node = 'LessThan2~339'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { LessThan2~336 LessThan2~339 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 11.400 ns out1~378 4 COMB LC2_C14 1 " "Info: 4: + IC(2.200 ns) + CELL(1.700 ns) = 11.400 ns; Loc. = LC2_C14; Fanout = 1; COMB Node = 'out1~378'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { LessThan2~339 out1~378 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 12.300 ns out1~380 5 COMB LC3_C14 1 " "Info: 5: + IC(0.000 ns) + CELL(0.900 ns) = 12.300 ns; Loc. = LC3_C14; Fanout = 1; COMB Node = 'out1~380'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { out1~378 out1~380 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 13.800 ns out1~370 6 COMB LC4_C14 1 " "Info: 6: + IC(0.000 ns) + CELL(1.500 ns) = 13.800 ns; Loc. = LC4_C14; Fanout = 1; COMB Node = 'out1~370'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { out1~380 out1~370 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 15.600 ns out1 7 REG LC1_C14 3 " "Info: 7: + IC(0.600 ns) + CELL(1.200 ns) = 15.600 ns; Loc. = LC1_C14; Fanout = 3; REG Node = 'out1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { out1~370 out1 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.900 ns ( 63.46 % ) " "Info: Total cell delay = 9.900 ns ( 63.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.700 ns ( 36.54 % ) " "Info: Total interconnect delay = 5.700 ns ( 36.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "15.600 ns" { lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] LessThan2~336 LessThan2~339 out1~378 out1~380 out1~370 out1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "15.600 ns" { lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] {} LessThan2~336 {} LessThan2~339 {} out1~378 {} out1~380 {} out1~370 {} out1 {} } { 0.000ns 2.300ns 0.600ns 2.200ns 0.000ns 0.000ns 0.600ns } { 0.000ns 2.300ns 2.300ns 1.700ns 0.900ns 1.500ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 21 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 21; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns out1 2 REG LC1_C14 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C14; Fanout = 3; REG Node = 'out1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk out1 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk out1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} out1 {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 21 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 21; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:c1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC2_C17 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_C17; Fanout = 5; REG Node = 'lpm_counter:c1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk out1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} out1 {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "15.600 ns" { lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] LessThan2~336 LessThan2~339 out1~378 out1~380 out1~370 out1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "15.600 ns" { lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] {} LessThan2~336 {} LessThan2~339 {} out1~378 {} out1~380 {} out1~370 {} out1 {} } { 0.000ns 2.300ns 0.600ns 2.200ns 0.000ns 0.000ns 0.600ns } { 0.000ns 2.300ns 2.300ns 1.700ns 0.900ns 1.500ns 1.200ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk out1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} out1 {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} lpm_counter:c1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk outclk out1 13.900 ns register " "Info: tco from clock \"clk\" to destination pin \"outclk\" through register \"out1\" is 13.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 21 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 21; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns out1 2 REG LC1_C14 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C14; Fanout = 3; REG Node = 'out1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk out1 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk out1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} out1 {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.500 ns + Longest register pin " "Info: + Longest register to pin delay is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out1 1 REG LC1_C14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C14; Fanout = 3; REG Node = 'out1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { out1 } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(5.100 ns) 7.500 ns outclk 2 PIN PIN_27 0 " "Info: 2: + IC(2.400 ns) + CELL(5.100 ns) = 7.500 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'outclk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { out1 outclk } "NODE_NAME" } } { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/divide/divide.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 68.00 % ) " "Info: Total cell delay = 5.100 ns ( 68.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns ( 32.00 % ) " "Info: Total interconnect delay = 2.400 ns ( 32.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { out1 outclk } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "7.500 ns" { out1 {} outclk {} } { 0.000ns 2.400ns } { 0.000ns 5.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk out1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} out1 {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { out1 outclk } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "7.500 ns" { out1 {} outclk {} } { 0.000ns 2.400ns } { 0.000ns 5.100ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Peak virtual memory: 124 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 22 19:33:29 2009 " "Info: Processing ended: Wed Apr 22 19:33:29 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}