led.tan.summary

来自「用VHDL开发的数字钟资料 完整的实验代码」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.500 ns
From           : m[0]
To             : c[2]
From Clock     : --
To Clock       : m[1]
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 29.300 ns
From           : d1[6]
To             : led7[6]
From Clock     : h1[1]
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.100 ns
From           : h1[2]
To             : d1[1]
From Clock     : --
To Clock       : h1[1]
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : a[0]
To             : a[2]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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