led.vhd

用VHDL开发的数字钟资料 完整的实验代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity led is
port
 (
  clk    : in std_logic;        --2.5MHZ
   s:   in std_logic_vector(3 downto 0);
  s1:   in std_logic_vector(3 downto 0);
  m:   in std_logic_vector(3 downto 0);
  m1:   in std_logic_vector(3 downto 0);
  h:   in std_logic_vector(3 downto 0);
  h1:   in std_logic_vector(3 downto 0);
   l:     out std_logic_vector(2 downto 0);
  led7   : out std_logic_vector(6 downto 0)
 );
end entity;
architecture one of led is
signal a:std_logic_vector(2 downto 0);
signal b:  std_logic_vector(6 downto 0);
signal b1:  std_logic_vector(6 downto 0);
signal c:  std_logic_vector(6 downto 0);
signal c1:  std_logic_vector(6 downto 0);
signal d:  std_logic_vector(6 downto 0);
signal d1:  std_logic_vector(6 downto 0);
begin
 p1:process(d1,d,c1,c,b1,b,clk,a)
     begin
   if (rising_edge(clk)) then  
        if a<7  then  a<=a+1;  
          elsif a=7   then   a<="000"; 
        end if;
 end if;
 case a is 
when "111" =>  led7<=d1;
when "110" =>  led7<=d;
when "101" =>  led7<="1000000";
when "100" =>  led7<=c1;
when "011" =>  led7<=c;
when "010" =>  led7<="1000000";
when "001" =>  led7<=b1;
when "000" =>  led7<=b;
when others => null;
end case;
l<=a;
end process p1;
p2:process( h1,h )
begin
case h1 is
when "0000" => d1<="0111111";
when "0001" => d1<="0000110";
when "0010" => d1<="1011011";
when "0011" => d1<="1001111";
when "0100" => d1<="1100110";
when "0101" => d1<="1101101";
when "0110" => d1<="1111101";
when "0111" => d1<="0000111";
when "1000" => d1<="1111111";
when "1001" => d1<="1101111";
when others => null;
end case;
case h is
when "0000" => d<="0111111";
when "0001" => d<="0000110";
when "0010" => d<="1011011";
when "0011" => d<="1001111";
when "0100" => d<="1100110";
when "0101" => d<="1101101";
when "0110" => d<="1111101";
when "0111" => d<="0000111";
when "1000" => d<="1111111";
when "1001" => d<="1101111";
when others => null;
end case;
end process p2;
min:process( m1,m )
begin
case m1 is
when "0000" => c1<="0111111";
when "0001" => c1<="0000110";
when "0010" => c1<="1011011";
when "0011" => c1<="1001111";
when "0100" => c1<="1100110";
when "0101" => c1<="1101101";
when "0110" => c1<="1111101";
when "0111" => c1<="0000111";
when "1000" => c1<="1111111";
when "1001" => c1<="1101111";
when others => null;
end case;
case m is
when "0000" => c<="0111111";
when "0001" => c<="0000110";
when "0010" => c<="1011011";
when "0011" => c<="1001111";
when "0100" => c<="1100110";
when "0101" => c<="1101101";
when "0110" => c<="1111101";
when "0111" => c<="0000111";
when "1000" => c<="1111111";
when "1001" => c<="1101111";
when others => null;
end case;
end process min;
sex:process( s1,s )
begin
case s1 is
when "0000" => b1<="0111111";
when "0001" => b1<="0000110";
when "0010" => b1<="1011011";
when "0011" => b1<="1001111";
when "0100" => b1<="1100110";
when "0101" => b1<="1101101";
when "0110" => b1<="1111101";
when "0111" => b1<="0000111";
when "1000" => b1<="1111111";
when "1001" => b1<="1101111";
when others => null;
end case;
case s is
when "0000" => b<="0111111";
when "0001" => b<="0000110";
when "0010" => b<="1011011";
when "0011" => b<="1001111";
when "0100" => b<="1100110";
when "0101" => b<="1101101";
when "0110" => b<="1111101";
when "0111" => b<="0000111";
when "1000" => b<="1111111";
when "1001" => b<="1101111";
when others => null;
end case;
end process sex;
end one;