divide.vhd

用VHDL开发的数字钟资料 完整的实验代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity divide is
port
 (
  clk    : in std_logic;
  outclk   : out std_logic
 );
end entity;
architecture one of divide is
signal c1:integer range 0 to 625000 ;
signal out1:std_logic;
begin
  p1:process (clk,out1)       --odd
 begin
 if (rising_edge(clk)) then  c1<=c1+1;
       if c1<=312500  then out1<='1';
     elsif c1>312500 and c1<625000 then
            out1<='0';
       elsif c1=625000 then c1<=0;
     end if;
         end if;
   end process p1;
   outclk<=out1;
 end one;