clock.hier_info

用VHDL开发的数字钟资料 完整的实验代码

|clock
clk0 => divide:u1.clk
clk1 => led:u3.clk
rst0 => time:u2.rst
en0 => time:u2.en
cout <= divide:u1.outclk
l1[0] <= led:u3.l[0]
l1[1] <= led:u3.l[1]
l1[2] <= led:u3.l[2]
led71[0] <= led:u3.led7[0]
led71[1] <= led:u3.led7[1]
led71[2] <= led:u3.led7[2]
led71[3] <= led:u3.led7[3]
led71[4] <= led:u3.led7[4]
led71[5] <= led:u3.led7[5]
led71[6] <= led:u3.led7[6]


|clock|divide:u1
clk => c1[19].CLK
clk => c1[18].CLK
clk => c1[17].CLK
clk => c1[16].CLK
clk => c1[15].CLK
clk => c1[14].CLK
clk => c1[13].CLK
clk => c1[12].CLK
clk => c1[11].CLK
clk => c1[10].CLK
clk => c1[9].CLK
clk => c1[8].CLK
clk => c1[7].CLK
clk => c1[6].CLK
clk => c1[5].CLK
clk => c1[4].CLK
clk => c1[3].CLK
clk => c1[2].CLK
clk => c1[1].CLK
clk => c1[0].CLK
clk => out1.CLK
outclk <= out1.DB_MAX_OUTPUT_PORT_TYPE


|clock|time:u2
clk => a[3].CLK
clk => a[2].CLK
clk => a[1].CLK
clk => a[0].CLK
clk => b[3].CLK
clk => b[2].CLK
clk => b[1].CLK
clk => b[0].CLK
clk => cmin.CLK
rst => a[3].ACLR
rst => a[2].ACLR
rst => a[1].ACLR
rst => a[0].ACLR
rst => b[3].ACLR
rst => b[2].ACLR
rst => b[1].ACLR
rst => b[0].ACLR
rst => c[3].ACLR
rst => c[2].ACLR
rst => c[1].ACLR
rst => c[0].ACLR
rst => d[3].ACLR
rst => d[2].ACLR
rst => d[1].ACLR
rst => d[0].ACLR
rst => e[3].ACLR
rst => e[2].ACLR
rst => e[1].ACLR
rst => e[0].ACLR
rst => f[3].ACLR
rst => f[2].ACLR
rst => f[1].ACLR
rst => f[0].ACLR
rst => cmin.ENA
rst => chour.ENA
en => chour~4.OUTPUTSELECT
en => cmin~4.OUTPUTSELECT
en => a[3].ENA
en => a[2].ENA
en => a[1].ENA
en => a[0].ENA
en => b[3].ENA
en => b[2].ENA
en => b[1].ENA
en => b[0].ENA
en => c[3].ENA
en => c[2].ENA
en => c[1].ENA
en => c[0].ENA
en => d[3].ENA
en => d[2].ENA
en => d[1].ENA
en => d[0].ENA
en => f[0].ENA
en => e[3].ENA
en => e[2].ENA
en => e[1].ENA
en => e[0].ENA
en => f[3].ENA
en => f[2].ENA
en => f[1].ENA
s[0] <= a[0].DB_MAX_OUTPUT_PORT_TYPE
s[1] <= a[1].DB_MAX_OUTPUT_PORT_TYPE
s[2] <= a[2].DB_MAX_OUTPUT_PORT_TYPE
s[3] <= a[3].DB_MAX_OUTPUT_PORT_TYPE
s1[0] <= b[0].DB_MAX_OUTPUT_PORT_TYPE
s1[1] <= b[1].DB_MAX_OUTPUT_PORT_TYPE
s1[2] <= b[2].DB_MAX_OUTPUT_PORT_TYPE
s1[3] <= b[3].DB_MAX_OUTPUT_PORT_TYPE
m[0] <= c[0].DB_MAX_OUTPUT_PORT_TYPE
m[1] <= c[1].DB_MAX_OUTPUT_PORT_TYPE
m[2] <= c[2].DB_MAX_OUTPUT_PORT_TYPE
m[3] <= c[3].DB_MAX_OUTPUT_PORT_TYPE
m1[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
m1[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
m1[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
m1[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
h[0] <= e[0].DB_MAX_OUTPUT_PORT_TYPE
h[1] <= e[1].DB_MAX_OUTPUT_PORT_TYPE
h[2] <= e[2].DB_MAX_OUTPUT_PORT_TYPE
h[3] <= e[3].DB_MAX_OUTPUT_PORT_TYPE
h1[0] <= f[0].DB_MAX_OUTPUT_PORT_TYPE
h1[1] <= f[1].DB_MAX_OUTPUT_PORT_TYPE
h1[2] <= f[2].DB_MAX_OUTPUT_PORT_TYPE
h1[3] <= f[3].DB_MAX_OUTPUT_PORT_TYPE


|clock|led:u3
clk => a[2].CLK
clk => a[1].CLK
clk => a[0].CLK
s[0] => Mux14.IN19
s[0] => Mux13.IN19
s[0] => Mux12.IN19
s[0] => Mux11.IN19
s[0] => Mux10.IN19
s[0] => Mux9.IN19
s[0] => Mux8.IN19
s[0] => Mux0.IN19
s[1] => Mux14.IN18
s[1] => Mux13.IN18
s[1] => Mux12.IN18
s[1] => Mux11.IN18
s[1] => Mux10.IN18
s[1] => Mux9.IN18
s[1] => Mux8.IN18
s[1] => Mux0.IN18
s[2] => Mux14.IN17
s[2] => Mux13.IN17
s[2] => Mux12.IN17
s[2] => Mux11.IN17
s[2] => Mux10.IN17
s[2] => Mux9.IN17
s[2] => Mux8.IN17
s[2] => Mux0.IN17
s[3] => Mux14.IN16
s[3] => Mux13.IN16
s[3] => Mux12.IN16
s[3] => Mux11.IN16
s[3] => Mux10.IN16
s[3] => Mux9.IN16
s[3] => Mux8.IN16
s[3] => Mux0.IN16
s1[0] => Mux22.IN19
s1[0] => Mux21.IN19
s1[0] => Mux20.IN19
s1[0] => Mux19.IN19
s1[0] => Mux18.IN19
s1[0] => Mux17.IN19
s1[0] => Mux16.IN19
s1[0] => Mux15.IN19
s1[1] => Mux22.IN18
s1[1] => Mux21.IN18
s1[1] => Mux20.IN18
s1[1] => Mux19.IN18
s1[1] => Mux18.IN18
s1[1] => Mux17.IN18
s1[1] => Mux16.IN18
s1[1] => Mux15.IN18
s1[2] => Mux22.IN17
s1[2] => Mux21.IN17
s1[2] => Mux20.IN17
s1[2] => Mux19.IN17
s1[2] => Mux18.IN17
s1[2] => Mux17.IN17
s1[2] => Mux16.IN17
s1[2] => Mux15.IN17
s1[3] => Mux22.IN16
s1[3] => Mux21.IN16
s1[3] => Mux20.IN16
s1[3] => Mux19.IN16
s1[3] => Mux18.IN16
s1[3] => Mux17.IN16
s1[3] => Mux16.IN16
s1[3] => Mux15.IN16
m[0] => Mux30.IN19
m[0] => Mux29.IN19
m[0] => Mux28.IN19
m[0] => Mux27.IN19
m[0] => Mux26.IN19
m[0] => Mux25.IN19
m[0] => Mux24.IN19
m[0] => Mux23.IN19
m[1] => Mux30.IN18
m[1] => Mux29.IN18
m[1] => Mux28.IN18
m[1] => Mux27.IN18
m[1] => Mux26.IN18
m[1] => Mux25.IN18
m[1] => Mux24.IN18
m[1] => Mux23.IN18
m[2] => Mux30.IN17
m[2] => Mux29.IN17
m[2] => Mux28.IN17
m[2] => Mux27.IN17
m[2] => Mux26.IN17
m[2] => Mux25.IN17
m[2] => Mux24.IN17
m[2] => Mux23.IN17
m[3] => Mux30.IN16
m[3] => Mux29.IN16
m[3] => Mux28.IN16
m[3] => Mux27.IN16
m[3] => Mux26.IN16
m[3] => Mux25.IN16
m[3] => Mux24.IN16
m[3] => Mux23.IN16
m1[0] => Mux38.IN19
m1[0] => Mux37.IN19
m1[0] => Mux36.IN19
m1[0] => Mux35.IN19
m1[0] => Mux34.IN19
m1[0] => Mux33.IN19
m1[0] => Mux32.IN19
m1[0] => Mux31.IN19
m1[1] => Mux38.IN18
m1[1] => Mux37.IN18
m1[1] => Mux36.IN18
m1[1] => Mux35.IN18
m1[1] => Mux34.IN18
m1[1] => Mux33.IN18
m1[1] => Mux32.IN18
m1[1] => Mux31.IN18
m1[2] => Mux38.IN17
m1[2] => Mux37.IN17
m1[2] => Mux36.IN17
m1[2] => Mux35.IN17
m1[2] => Mux34.IN17
m1[2] => Mux33.IN17
m1[2] => Mux32.IN17
m1[2] => Mux31.IN17
m1[3] => Mux38.IN16
m1[3] => Mux37.IN16
m1[3] => Mux36.IN16
m1[3] => Mux35.IN16
m1[3] => Mux34.IN16
m1[3] => Mux33.IN16
m1[3] => Mux32.IN16
m1[3] => Mux31.IN16
h[0] => Mux46.IN19
h[0] => Mux45.IN19
h[0] => Mux44.IN19
h[0] => Mux43.IN19
h[0] => Mux42.IN19
h[0] => Mux41.IN19
h[0] => Mux40.IN19
h[0] => Mux39.IN19
h[1] => Mux46.IN18
h[1] => Mux45.IN18
h[1] => Mux44.IN18
h[1] => Mux43.IN18
h[1] => Mux42.IN18
h[1] => Mux41.IN18
h[1] => Mux40.IN18
h[1] => Mux39.IN18
h[2] => Mux46.IN17
h[2] => Mux45.IN17
h[2] => Mux44.IN17
h[2] => Mux43.IN17
h[2] => Mux42.IN17
h[2] => Mux41.IN17
h[2] => Mux40.IN17
h[2] => Mux39.IN17
h[3] => Mux46.IN16
h[3] => Mux45.IN16
h[3] => Mux44.IN16
h[3] => Mux43.IN16
h[3] => Mux42.IN16
h[3] => Mux41.IN16
h[3] => Mux40.IN16
h[3] => Mux39.IN16
h1[0] => Mux54.IN19
h1[0] => Mux53.IN19
h1[0] => Mux52.IN19
h1[0] => Mux51.IN19
h1[0] => Mux50.IN19
h1[0] => Mux49.IN19
h1[0] => Mux48.IN19
h1[0] => Mux47.IN19
h1[1] => Mux54.IN18
h1[1] => Mux53.IN18
h1[1] => Mux52.IN18
h1[1] => Mux51.IN18
h1[1] => Mux50.IN18
h1[1] => Mux49.IN18
h1[1] => Mux48.IN18
h1[1] => Mux47.IN18
h1[2] => Mux54.IN17
h1[2] => Mux53.IN17
h1[2] => Mux52.IN17
h1[2] => Mux51.IN17
h1[2] => Mux50.IN17
h1[2] => Mux49.IN17
h1[2] => Mux48.IN17
h1[2] => Mux47.IN17
h1[3] => Mux54.IN16
h1[3] => Mux53.IN16
h1[3] => Mux52.IN16
h1[3] => Mux51.IN16
h1[3] => Mux50.IN16
h1[3] => Mux49.IN16
h1[3] => Mux48.IN16
h1[3] => Mux47.IN16
l[0] <= a[0].DB_MAX_OUTPUT_PORT_TYPE
l[1] <= a[1].DB_MAX_OUTPUT_PORT_TYPE
l[2] <= a[2].DB_MAX_OUTPUT_PORT_TYPE
led7[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
led7[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
led7[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
led7[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
led7[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
led7[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
led7[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE