clock.fnsim.qmsg

用VHDL开发的数字钟资料 完整的实验代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 22 20:20:38 2009 " "Info: Processing started: Wed Apr 22 20:20:38 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/yulin/clock/clock/clock.vhd " "Warning: Can't analyze file -- file E:/yulin/clock/clock/clock.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "time.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file time.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 time-one " "Info: Found design unit 1: time-one" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 time " "Info: Found entity 1: time" {  } { { "time.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/time.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file led.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 led-one " "Info: Found design unit 1: led-one" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 led " "Info: Found entity 1: led" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WSGN_MEGAFN_REPLACE" "divide G:/edatest/yulin/yulin/clock/clock/divide.vhd " "Warning: Entity \"divide\" obtained from \"G:/edatest/yulin/yulin/clock/clock/divide.vhd\" instead of from Quartus II megafunction library" {  } {  } 0 0 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus II megafunction library" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divide.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file divide.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide-one " "Info: Found design unit 1: divide-one" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 divide " "Info: Found entity 1: divide" {  } { { "divide.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/divide.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "clock.vhd 2 1 " "Warning: Using design file clock.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-one " "Info: Found design unit 1: clock-one" {  } { { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "led7 clock.vhd(12) " "Warning (10541): VHDL Signal Declaration warning at clock.vhd(12): used implicit default value for signal \"led7\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 12 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "l\[2\] clock.vhd(11) " "Warning (10034): Output port \"l\[2\]\" at clock.vhd(11) has no driver" {  } { { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 11 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "l\[1\] clock.vhd(11) " "Warning (10034): Output port \"l\[1\]\" at clock.vhd(11) has no driver" {  } { { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 11 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "l\[0\] clock.vhd(11) " "Warning (10034): Output port \"l\[0\]\" at clock.vhd(11) has no driver" {  } { { "clock.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 11 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide divide:u1 " "Info: Elaborating entity \"divide\" for hierarchy \"divide:u1\"" {  } { { "clock.vhd" "u1" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 54 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "time time:u2 " "Info: Elaborating entity \"time\" for hierarchy \"time:u2\"" {  } { { "clock.vhd" "u2" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 55 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led led:u3 " "Info: Elaborating entity \"led\" for hierarchy \"led:u3\"" {  } { { "clock.vhd" "u3" { Text "G:/edatest/yulin/yulin/clock/clock/clock.vhd" 56 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "d1 led.vhd(48) " "Warning (10631): VHDL Process Statement warning at led.vhd(48): inferring latch(es) for signal or variable \"d1\", which holds its previous value in one or more paths through the process" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "d led.vhd(48) " "Warning (10631): VHDL Process Statement warning at led.vhd(48): inferring latch(es) for signal or variable \"d\", which holds its previous value in one or more paths through the process" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 48 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "c1 led.vhd(77) " "Warning (10631): VHDL Process Statement warning at led.vhd(77): inferring latch(es) for signal or variable \"c1\", which holds its previous value in one or more paths through the process" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "c led.vhd(77) " "Warning (10631): VHDL Process Statement warning at led.vhd(77): inferring latch(es) for signal or variable \"c\", which holds its previous value in one or more paths through the process" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b1 led.vhd(106) " "Warning (10631): VHDL Process Statement warning at led.vhd(106): inferring latch(es) for signal or variable \"b1\", which holds its previous value in one or more paths through the process" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b led.vhd(106) " "Warning (10631): VHDL Process Statement warning at led.vhd(106): inferring latch(es) for signal or variable \"b\", which holds its previous value in one or more paths through the process" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b\[0\] led.vhd(106) " "Info (10041): Inferred latch for \"b\[0\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b\[1\] led.vhd(106) " "Info (10041): Inferred latch for \"b\[1\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b\[2\] led.vhd(106) " "Info (10041): Inferred latch for \"b\[2\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b\[3\] led.vhd(106) " "Info (10041): Inferred latch for \"b\[3\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b\[4\] led.vhd(106) " "Info (10041): Inferred latch for \"b\[4\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b\[5\] led.vhd(106) " "Info (10041): Inferred latch for \"b\[5\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b\[6\] led.vhd(106) " "Info (10041): Inferred latch for \"b\[6\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b1\[0\] led.vhd(106) " "Info (10041): Inferred latch for \"b1\[0\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b1\[1\] led.vhd(106) " "Info (10041): Inferred latch for \"b1\[1\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b1\[2\] led.vhd(106) " "Info (10041): Inferred latch for \"b1\[2\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b1\[3\] led.vhd(106) " "Info (10041): Inferred latch for \"b1\[3\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b1\[4\] led.vhd(106) " "Info (10041): Inferred latch for \"b1\[4\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b1\[5\] led.vhd(106) " "Info (10041): Inferred latch for \"b1\[5\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "b1\[6\] led.vhd(106) " "Info (10041): Inferred latch for \"b1\[6\]\" at led.vhd(106)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 106 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "c\[0\] led.vhd(77) " "Info (10041): Inferred latch for \"c\[0\]\" at led.vhd(77)" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/clock/led.vhd" 77 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}