clock.map.summary

来自「用VHDL开发的数字钟资料 完整的实验代码」· SUMMARY 代码 · 共 9 行

Analysis & Synthesis Status : Successful - Thu Apr 23 11:39:52 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : FLEX10K
Total logic elements : 255
Total pins : 15
Total memory bits : 0