clock.tan.summary

用VHDL开发的数字钟资料 完整的实验代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.600 ns
From           : en0
To             : time:u2|b[3]
From Clock     : --
To Clock       : clk0
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 50.900 ns
From           : led:u3|d1[6]
To             : led71[6]
From Clock     : clk0
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 18.700 ns
From           : en0
To             : time:u2|e[3]
From Clock     : --
To Clock       : clk0
Failed Paths   : 0

Type           : Clock Setup: 'clk0'
Slack          : N/A
Required Time  : None
Actual Time    : 35.09 MHz ( period = 28.500 ns )
From           : divide:u1|c1[18]
To             : divide:u1|c1[6]
From Clock     : clk0
To Clock       : clk0
Failed Paths   : 0

Type           : Clock Setup: 'clk1'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : led:u3|a[1]
To             : led:u3|a[2]
From Clock     : clk1
To Clock       : clk1
Failed Paths   : 0

Type           : Clock Hold: 'clk0'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : time:u2|c[3]
To             : led:u3|c[0]
From Clock     : clk0
To Clock       : clk0
Failed Paths   : 150

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 150

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