clock.fit.summary

用VHDL开发的数字钟资料 完整的实验代码

Fitter Status : Successful - Thu Apr 23 11:40:05 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : FLEX10K
Device : EPF10K10LC84-4
Timing Models : Final
Total logic elements : 255 / 576 ( 44 % )
Total pins : 15 / 59 ( 25 % )
Total memory bits : 0 / 6,144 ( 0 % )