clock.vhd

用VHDL开发的数字钟资料 完整的实验代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clock is
port( clk0    : in std_logic;     --625KHZ
      clk1    : in std_logic;    --2.5MHZ
      rst0:in std_logic;         --0 high enable
      en0:in std_logic;          --high enable
      cout:out std_logic;
      l1:     out std_logic_vector(2 downto 0);
     led71  : out std_logic_vector(6 downto 0)
);
end entity clock;
architecture one of clock is
component divide
port
 (
  clk    : in std_logic;    --625KHZ
  outclk   : out std_logic   --1HZ
 );
end component;
component time
port
 (
  clk    : in std_logic;   --1HZ
  rst:in std_logic;
   en:in std_logic;
   s:   out std_logic_vector(3 downto 0);
  s1:   out std_logic_vector(3 downto 0);
  m:   out std_logic_vector(3 downto 0);
  m1:   out std_logic_vector(3 downto 0);
  h:   out std_logic_vector(3 downto 0);
  h1:   out std_logic_vector(3 downto 0)
 );
end component;
component led
port
 (
  clk    : in std_logic;     --2.5MHZ
   s:   in std_logic_vector(3 downto 0);
  s1:   in std_logic_vector(3 downto 0);
  m:   in std_logic_vector(3 downto 0);
  m1:   in std_logic_vector(3 downto 0);
  h:   in std_logic_vector(3 downto 0);
  h1:   in std_logic_vector(3 downto 0);
   l:     buffer std_logic_vector(2 downto 0);
  led7   : out std_logic_vector(6 downto 0)
 );
end component;
signal a:std_logic;
signal z,y,x,w,v,u:std_logic_vector(3 downto 0);
begin
u1:divide port map(clk=>clk0,outclk=>a);
u2:time port map(clk=>a,rst=>rst0,en=>en0,s=>u,s1=>v,m=>w,m1=>x,h=>y,h1=>z);
u3:led port map(clk=>clk1,s=>u,s1=>v,m=>w,m1=>x,h=>y,h1=>z,l=>l1,led7=>led71);
cout<=a;
end one;