time.vhd

用VHDL开发的数字钟资料 完整的实验代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity time is
port
 (
  clk    : in std_logic;
  rst:in std_logic;
   en:in std_logic;
   s:   out std_logic_vector(3 downto 0);
  s1:   out std_logic_vector(3 downto 0);
  m:   out std_logic_vector(3 downto 0);
  m1:   out std_logic_vector(3 downto 0);
  h:   out std_logic_vector(3 downto 0);
  h1:   out std_logic_vector(3 downto 0)
 );
end entity;
architecture one of time is
signal cmin:std_logic;
signal chour:std_logic;
signal a: std_logic_vector(3 downto 0) ;
signal b: std_logic_vector(3 downto 0) ;
signal c: std_logic_vector(3 downto 0) ;
signal d: std_logic_vector(3 downto 0) ;
signal e: std_logic_vector(3 downto 0) ;
signal f: std_logic_vector(3 downto 0) ;
begin
p1:process(clk,rst)
begin
if rst='1'    then  a<=(others=>'0');  b<=(others=>'0'); 
elsif clk'event and clk='1'   then    
  if en='1'  then
     if a<9   then a<=a+1;   
             elsif   a=9    then  
        if  b<5  then  b<=b+1;   a<="0000"; cmin<='0';
        elsif  b=5   then   b<="0000"; a<="0000";cmin<='1';
        end if;
     end if;
  end if;
end if;
end process p1;
p2:process(cmin,rst)
 begin  
    if rst='1'    then  c<=(others=>'0'); d<=(others=>'0'); 
     elsif cmin'event and cmin='1' then   
      if en='1'  then
       if c<9  then  c<=c+1; 
             elsif  c=9  then
          if  d<5   then  d<=d+1; c<="0000";chour<='0';
             elsif  d=5  then  d<="0000"; c<="0000";chour<='1';
          end if;
       end if;
    end if;
   end if;
   end process p2;
 p3:process(chour,rst)
     begin  
    if rst='1'    then  e<=(others=>'0'); f<=(others=>'0'); 
     elsif chour'event and chour='1'   then 
       if en='1'  then        
         if f<2  then 
           if e<9  then   e<=e+1; 
            elsif e=9   then  f<=f+1; e<="0000";
           end if;
         elsif  f=2  then 
            if  e<3   then  e<=e+1;
            else  e<="0000";f<="0000";
            end if;
         end if;
    end if;
   end if;
end process p3;
s1<=b; s<=a;
m1<=d; m<=c;
h1<=f; h<=e;
end one;