time.map.rpt

来自「用VHDL开发的数字钟资料 完整的实验代码」· RPT 代码 · 共 261 行 · 第 1/2 页

; a_csnbuffer.inc                  ; yes             ; Megafunction    ; e:/quartus/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction    ; e:/quartus/libraries/megafunctions/a_csnbuffer.tdf         ;
; altshift.tdf                     ; yes             ; Megafunction    ; e:/quartus/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 75      ;
; Total combinational functions     ; 73      ;
;     -- Total 4-input functions    ; 28      ;
;     -- Total 3-input functions    ; 23      ;
;     -- Total 2-input functions    ; 19      ;
;     -- Total 1-input functions    ; 3       ;
;     -- Total 0-input functions    ; 0       ;
; Total registers                   ; 26      ;
; Total logic cells in carry chains ; 4       ;
; I/O pins                          ; 27      ;
; Maximum fan-out node              ; rst     ;
; Maximum fan-out                   ; 26      ;
; Total fan-out                     ; 323     ;
; Average fan-out                   ; 3.17    ;
+-----------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                     ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------+--------------+
; Compilation Hierarchy Node         ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                          ; Library Name ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------+--------------+
; |time                              ; 75 (71)     ; 26           ; 0           ; 27   ; 49 (45)      ; 2 (2)             ; 24 (24)          ; 4 (0)           ; 0 (0)      ; |time                                                        ; work         ;
;    |lpm_add_sub:Add4|              ; 4 (0)       ; 0            ; 0           ; 0    ; 4 (0)        ; 0 (0)             ; 0 (0)            ; 4 (0)           ; 0 (0)      ; |time|lpm_add_sub:Add4                                       ; work         ;
;       |addcore:adder|              ; 4 (1)       ; 0            ; 0           ; 0    ; 4 (1)        ; 0 (0)             ; 0 (0)            ; 4 (1)           ; 0 (0)      ; |time|lpm_add_sub:Add4|addcore:adder                         ; work         ;
;          |a_csnbuffer:result_node| ; 3 (3)       ; 0            ; 0           ; 0    ; 3 (3)        ; 0 (0)             ; 0 (0)            ; 3 (3)           ; 0 (0)      ; |time|lpm_add_sub:Add4|addcore:adder|a_csnbuffer:result_node ; work         ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 26    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 24    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 22    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------+
; Source assignments for lpm_add_sub:Add4|addcore:adder ;
+---------------------------+-------+------+------------+
; Assignment                ; Value ; From ; To         ;
+---------------------------+-------+------+------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103  ; -    ; -          ;
+---------------------------+-------+------+------------+


+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4 ;
+------------------------+-------------+----------------------------+
; Parameter Name         ; Value       ; Type                       ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH              ; 4           ; Untyped                    ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                    ;
; LPM_DIRECTION          ; ADD         ; Untyped                    ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                    ;
; LPM_PIPELINE           ; 0           ; Untyped                    ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                    ;
; REGISTERED_AT_END      ; 0           ; Untyped                    ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                    ;
; USE_CS_BUFFERS         ; 1           ; Untyped                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH         ;
; DEVICE_FAMILY          ; FLEX10K     ; Untyped                    ;
; USE_WYS                ; OFF         ; Untyped                    ;
; STYLE                  ; FAST        ; Untyped                    ;
; CBXI_PARAMETER         ; add_sub_njh ; Untyped                    ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE             ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Wed Apr 22 22:11:26 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off time -c time
Info: Found 2 design units, including 1 entities, in source file time.vhd
    Info: Found design unit 1: time-one
    Info: Found entity 1: time
Info: Elaborating entity "time" for the top level hierarchy
Info: Inferred 1 megafunctions from design logic
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add4"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add4"
Info: Instantiated megafunction "lpm_add_sub:Add4" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add4|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add4"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add4|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add4"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add4|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add4"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add4|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add4"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add4|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add4"
Info: Implemented 102 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 24 output pins
    Info: Implemented 75 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 180 megabytes
    Info: Processing ended: Wed Apr 22 22:11:31 2009
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:03