music2.tan.rpt

基于vhdl的音乐发生器源程序

Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off music2 -c music2
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk2" is an undefined clock
    Info: Assuming node "clk1" is an undefined clock
Info: Clock "clk2" has Internal fmax of 101.01 MHz between source register "speak:u2|lpm_counter:c_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" and destination register "speak:u2|lpm_counter:c_rtl_0|alt_counter_f10ke:wysi_counter|q[12]" (period= 9.9 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_E18; Fanout = 4; REG Node = 'speak:u2|lpm_counter:c_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC1_E17; Fanout = 2; COMB Node = 'speak:u2|Equal0~105'
        Info: 3: + IC(1.100 ns) + CELL(1.700 ns) = 5.900 ns; Loc. = LC1_E18; Fanout = 8; COMB Node = 'speak:u2|Equal0~106'
        Info: 4: + IC(1.100 ns) + CELL(1.000 ns) = 8.000 ns; Loc. = LC7_E20; Fanout = 2; REG Node = 'speak:u2|lpm_counter:c_rtl_0|alt_counter_f10ke:wysi_counter|q[12]'
        Info: Total cell delay = 4.700 ns ( 58.75 % )
        Info: Total interconnect delay = 3.300 ns ( 41.25 % )
    Info: - Smallest clock skew is -0.100 ns
        Info: + Shortest clock path from clock "clk2" to destination register is 7.600 ns
            Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_75; Fanout = 9; CLK Node = 'clk2'
            Info: 2: + IC(4.500 ns) + CELL(0.000 ns) = 7.600 ns; Loc. = LC7_E20; Fanout = 2; REG Node = 'speak:u2|lpm_counter:c_rtl_0|alt_counter_f10ke:wysi_counter|q[12]'
            Info: Total cell delay = 3.100 ns ( 40.79 % )
            Info: Total interconnect delay = 4.500 ns ( 59.21 % )
        Info: - Longest clock path from clock "clk2" to source register is 7.700 ns
            Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_75; Fanout = 9; CLK Node = 'clk2'
            Info: 2: + IC(4.600 ns) + CELL(0.000 ns) = 7.700 ns; Loc. = LC6_E18; Fanout = 4; REG Node = 'speak:u2|lpm_counter:c_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
            Info: Total cell delay = 3.100 ns ( 40.26 % )
            Info: Total interconnect delay = 4.600 ns ( 59.74 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: Clock "clk1" Internal fmax is restricted to 200.0 MHz between source register "tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[0]" and destination register "tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[7]"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.300 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E15; Fanout = 19; REG Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[0]'
            Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = LC1_E15; Fanout = 2; COMB Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT'
            Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 0.400 ns; Loc. = LC2_E15; Fanout = 2; COMB Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT'
            Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 0.600 ns; Loc. = LC3_E15; Fanout = 2; COMB Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT'
            Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 0.800 ns; Loc. = LC4_E15; Fanout = 2; COMB Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT'
            Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 1.000 ns; Loc. = LC5_E15; Fanout = 2; COMB Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT'
            Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 1.200 ns; Loc. = LC6_E15; Fanout = 2; COMB Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT'
            Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 1.400 ns; Loc. = LC7_E15; Fanout = 1; COMB Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT'
            Info: 9: + IC(0.000 ns) + CELL(0.900 ns) = 2.300 ns; Loc. = LC8_E15; Fanout = 43; REG Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[7]'
            Info: Total cell delay = 2.300 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk1" to destination register is 1.900 ns
                Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_80; Fanout = 8; CLK Node = 'clk1'
                Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC8_E15; Fanout = 43; REG Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[7]'
                Info: Total cell delay = 0.500 ns ( 26.32 % )
                Info: Total interconnect delay = 1.400 ns ( 73.68 % )
            Info: - Longest clock path from clock "clk1" to source register is 1.900 ns
                Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_80; Fanout = 8; CLK Node = 'clk1'
                Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_E15; Fanout = 19; REG Node = 'tone:u1|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[0]'
                Info: Total cell delay = 0.500 ns ( 26.32 % )
                Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: + Micro clock to output delay of source is 1.100 ns
        Info: + Micro setup delay of destination is 0.700 ns
Info: tco from clock "clk2" to destination pin "CQ" through register "speak:u2|q" is 19.000 ns
    Info: + Longest clock path from clock "clk2" to source register is 7.700 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_75; Fanout = 9; CLK Node = 'clk2'
        Info: 2: + IC(4.600 ns) + CELL(0.000 ns) = 7.700 ns; Loc. = LC8_E17; Fanout = 1; REG Node = 'speak:u2|q'
        Info: Total cell delay = 3.100 ns ( 40.26 % )
        Info: Total interconnect delay = 4.600 ns ( 59.74 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 10.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_E17; Fanout = 1; REG Node = 'speak:u2|q'
        Info: 2: + IC(1.700 ns) + CELL(8.500 ns) = 10.200 ns; Loc. = PIN_89; Fanout = 0; PIN Node = 'CQ'
        Info: Total cell delay = 8.500 ns ( 83.33 % )
        Info: Total interconnect delay = 1.700 ns ( 16.67 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 115 megabytes of memory during processing
    Info: Processing ended: Mon Dec 10 01:24:43 2007
    Info: Elapsed time: 00:00:01