graphics_pipeline.tan.rpt

Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was t

; Clock Setup: 'CLOCK_50'                                       ; N/A      ; None                             ; 241.60 MHz ( period = 4.139 ns ) ; Reset_Delay:d1|Cont[6]           ; Reset_Delay:d1|Cont[1]                                                                                       ; CLOCK_50                                       ; CLOCK_50                                       ; 0            ;
; Clock Hold: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk0'  ; 0.391 ns ; 25.20 MHz ( period = 39.682 ns ) ; N/A                              ; calcMvNormal:mvnormal3|inv2r[17] ; calcMvNormal:mvnormal3|inv2r[17]                                                                             ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                                  ;          ;                                  ;                                  ;                                  ;                                                                                                              ;                                                ;                                                ; 0            ;
+---------------------------------------------------------------+----------+----------------------------------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------+------------------------------------------------+------------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                  ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+------------+--------------+
; Clock Node Name                                ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset     ; Phase offset ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+------------+--------------+
; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 25.2 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 14                    ; 15                  ; -2.384 ns  ;              ;
; VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 ;                    ; PLL output ; 25.2 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 14                    ; 15                  ; -12.306 ns ;              ;
; CLOCK_27                                       ;                    ; User Pin   ; 27.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A        ;              ;
; CLOCK_50                                       ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A        ;              ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+---------------------+-----------------------------------+------------------------------------------------+------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                ; To                                ; From Clock                                     ; To Clock                                       ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------+-----------------------------------+------------------------------------------------+------------------------------------------------+-----------------------------+---------------------------+-------------------------+