rasterizer_11_07_2008_18_46.v.bak

Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was t

`define box 5'd9

module Rasterizer(clk, reset, x1, y1, x2, y2, x3, y3, pixelOut, out_pixel_x, out_pixel_y, stall, done);

input clk;
input reset;
input stall;

input wire signed[8:0] x1, x2, x3, y1, y2, y3;

output wire pixelOut;
assign pixelOut = (reset & ~done) | (state == 5'd7 && ((p3[17] == 0 && c3[17] == 1 && p3 > -c3) || (p3[17] == 0 && c3[17] == 0) || (p3[17] == 1 && c3[17] == 0 && c3 > -p3) || (p3[17] != c3[17] && p3 == -c3)));

output [9:0] out_pixel_x;
output [9:0] out_pixel_y;

reg [4:0] state;
output reg done;
reg [17:0] c1, c2, c3;
reg [4:0] i,j;
reg [17:0] p1, p2, p3;

parameter exit = 5'd15;

wire signed[17:0] wire1, wire2, wire3;
wire signed [8:0] in1a, in1b, in2a, in2b;

wire [8:0] xmin, ymin;
assign xmin = (x1 <= x2 & x1 <= x3) ? x1 : (x2 <= x1 & x2 <= x3) ? x2 : x3;
assign ymin = (y1 <= y2 & y1 <= y3) ? y1 : (y2 <= y1 & y2 <= y3) ? y2 : y3;

assign in1a = 	(state == 5'd1 || state == 5'd4) ? (y1-y2) : 
				(state == 5'd2 || state == 5'd5) ? (y3-y1) : 
				(state == 5'd3 || state == 5'd6) ? (y2-y3) : 0;
				
assign in1b = 	(state == 5'd1 ) ? x1-xmin : 
				(state == 5'd2 ) ? x3-xmin : 
				(state == 5'd3 ) ? x2-xmin : 
				(state == 5'd4 ) ? i  :
				(state == 5'd5 ) ? i  :
				(state == 5'd6 ) ? i  : 0;
				
assign in2a = 	(state == 5'd1 || state == 5'd4) ? (x1-x2) : 
				(state == 5'd2 || state == 5'd5) ? (x3-x1) : 
				(state == 5'd3 || state == 5'd6) ? (x2-x3) : 0;
								
assign in2b = 	(state == 5'd1 ) ? y1-ymin : 
				(state == 5'd2 ) ? y3-ymin : 
				(state == 5'd3 ) ? y2-ymin : 
				(state == 5'd4 ) ? j  :
				(state == 5'd5 ) ? j  :
				(state == 5'd6 ) ? j  : 0;


signed_mult_2 mult2(.a(in1a), .b(in1b), .out(wire1));
signed_mult_2 mult3(.a(in2a), .b(in2b), .out(wire2));


assign wire3 = wire1 - wire2;

assign out_pixel_x = xmin + i;
assign out_pixel_y = 240 - (ymin + j);

/* Note: vertice inputs are normalized to bounding box, where (0,0) is
bottom left corner*/
always@(posedge clk) begin
if (stall)
	begin
		i <= i;
        j <= j;
        c1 <= c1;
        c2 <= c2;
        c3 <= c3;
        state <= state;
        p1 <= p1;
        p2 <= p2;
        p3 <= p3;
        
        done <= done;
	end
else
begin
if(reset) begin
	state <= 5'd0;
	i <= 5'd0;
	j <= 5'd0;
	done <= 1'b0;
end
else begin
    /* Go through each pixel and compare to the three equations */
    case(state)
        0:
        begin
            i <= 0;
            j <= 0;
            c1 <= 0;
            c2 <= 0;
            c3 <= 0;
            p1 <= 0;
            p2 <= 0;
            p3 <= 0;
            done <= 1'b0;
            state <= 5'd1;
        end
        1:
        begin
            c1 <= -wire3; /*(y1-y2)*x1 - (x1-x2)*y1;*/
            state <= 5'd2;
        end
        2:
        begin
            c2 <= -wire3; //(y3-y1)*x3 - (x3-x1)*y3;
            state <= 5'd3;
        end
        3:
        begin
            c3 <= -wire3; //(y2-y3)*x2 - (x2-x3)*y2;
            state <= 5'd4;
        end
        4:
        begin
			p1 <= wire3; //(y1-y2)*i - (x1-x2)*j;
			state <= 5'd5;
			//pixelOut <= 1'b0;
		end
        5:
        begin
			if( (p1[17] == 0 && c1[17] == 1 && p1 > -c1) || (p1[17] == 0 && c1[17] == 0) || (p1[17] == 1 && c1[17] == 0 && c1 > -p1) || (p1[17] != c1[17] && p1 == -c1)) begin
                state <= 5'd6;
                p2 <= wire3; //(y3-y1)*i - (x3-x1)*j;
            end
            else begin
            //pixelOut <= 1'b0;
				if(i == 5'd9 && j == 5'd9)
					state <= exit;
                else begin
					if(i < 5'd9)
						i <= i + 5'd1;
					else begin
						j <= j + 5'd1;
						i <= 5'd0;
					end
					state <= 5'd4;
				end
			end
        end
        6:
        begin
            if( (p2[17] == 0 && c2[17] == 1 && p2 > -c2) || (p2[17] == 0 && c2[17] == 0) || (p2[17] == 1 && c2[17] == 0 && c2 > -p2) || (p2[17] != c2[17] && p2 == -c2))
            begin
				p3 <= wire3; //(y2-y3)*i - (x2-x3)*j;
                state <= 5'd7;
            end
            else begin
            //pixelOut <= 1'b0;
				if(i == 5'd9 && j == 5'd9)
					state <= exit;
                else begin
					if(i < 5'd9)
						i <= i + 5'd1;
					else begin
						j <= j + 5'd1;
						i <= 5'd0;
					end
					state <= 5'd4;
				end
			end
        end
        7:
        begin
//            if( p3[16:0] > c3[16:0] )
//                pixelOut <= 1'b1;
//            else
//                pixelOut <= 1'b0;

			if(i == 5'd9 && j == 5'd9)
				state <= exit;
            else begin
				if(i < 5'd9)
					i <= i + 5'd1;
				else begin
					j <= j + 5'd1;
					i <= 5'd0;
				end
				state <= 5'd4;
			end
		end
        exit:
        begin
            done <= 1'b1;
            //state <= 5'd0;
            //i <= 5'd0;
            //j <= 5'd0;
        end
	endcase
end //else
end //else
end //always

endmodule


////// NEED TO PASS A WRITE ENABLE OUT FOR THE SRAM
//
//
//module Rasterizer	(
//						clock,
//						reset,
//						
//						vertex1_x,
//						vertex1_y, 
//						
//						vertex2_x, 
//						vertex2_y, 
//						
//						vertex3_x, 
//						vertex3_y, 
//						
//						out_fragment_x, 
//						out_fragment_y, 
//						fragment_c,
//						
//						stallOUT,
//						stallIN,
//						
//						out
//					);
//			
//output [26:0] out;
//wire [26:0] out;
//
//assign out = fragment_x;
//					
//input clock;
//input reset;
//
//input signed[26:0] vertex1_x;
//input signed[26:0] vertex1_y;
//
//input signed[26:0] vertex2_x;
//input signed[26:0] vertex2_y;
//
//input signed[26:0] vertex3_x;
//input signed[26:0] vertex3_y;
//
//output [9:0] out_fragment_x;
//output [9:0] out_fragment_y;
//output [15:0] fragment_c;
//
//wire [9:0] out_fragment_x;
//wire [9:0] out_fragment_y;
//
//assign out_fragment_x = {2'b00, fragment_x[26:19]};
//assign out_fragment_y = {2'b00, fragment_y[26:19]};
//
//reg signed[26:0] fragment_x;
//reg signed[26:0] fragment_y;
//reg signed[15:0] fragment_c;
//
//input stallIN;
//wire stallIN;
//
//output stallOUT;
//reg stallOUT;
//
//reg [1:0] setup_counter;
//
//reg signed[26:0] xMin, xMax;
//reg signed[26:0] yMin, yMax;
//
//wire signed [26:0] r_minus_r3_x, r_minus_r3_y;
//
//wire signed [26:0] x1_x3, x2_x3, y1_y3, y2_y3;
//
//wire signed [26:0] det1, det2;
//reg signed [26:0] det;
//
//wire signed [26:0] lambda1, lambda2, lambda3;
//
//wire signed [26:0] a,b,d,e;
//reg signed [26:0] c,f;
//
//assign r_minus_r3_x = (fragment_x - vertex3_x) ;
//assign r_minus_r3_y = (fragment_y - vertex3_y) ;
//
//assign x1_x3 = (vertex1_x - vertex3_x) ;
//assign x2_x3 = (vertex2_x - vertex3_x) ;
//
//assign y1_y3 = (vertex1_y - vertex3_y) ;
//assign y2_y3 = (vertex2_y - vertex3_y) ;
//
//signed_mult_8 s1(det1, x1_x3, y2_y3);
//signed_mult_8 s2(det2, x2_x3, y1_y3);
//
//signed_mult_8 s3(a, y2_y3, r_minus_r3_x);
//signed_mult_8 s4(b, x2_x3, r_minus_r3_y);
//
//signed_mult_8 s5(d, y1_y3, r_minus_r3_x);
//signed_mult_8 s6(e, x1_x3, r_minus_r3_y);
//
//signed_mult_8 s7(lambda1, c, 27'b100000000000001100000000000);//27'b000000010000000000000000000 / det);
//signed_mult_8 s8(lambda2, f, 27'b100000000000001100000000000);//27'b000000010000000000000000000 / det);
//
//assign lambda3 = 27'b000000010000000000000000000 - lambda1 - lambda2;
//
//always @(posedge clock)
//begin
//	if (reset)
//	begin
//		stallOUT <= 1'b0;
//		
//		fragment_x <= 27'd0;
//		fragment_y <= 27'd0;
//		fragment_c <= 16'b0;
//		
//		xMin <= 10'b0;
//		xMax <= 10'b0;
//		
//		yMin <= 10'b0;
//		yMax <= 10'b0;
//		
//		setup_counter <= 2'b00;
//		
//		det <= 0;
//		c <= 0;
//		f <= 0;
//	end
//	
//	else if (stallOUT & !stallIN)
//	begin
//		if (setup_counter == 2'b00)
//		begin
//			det <= det1 - det2;
//			
//			c <= a - b;
//			f <= e - d;
//		
//			setup_counter <= 2'b01;
//		end
//		
//		else
//		begin
//			c <= c;
//			f <= f;
//			det <= det;
//			
//			setup_counter <= 2'b00;
//	
//			if (fragment_y <= yMax)
//			begin
//				if (fragment_x < xMax)
//				begin
//					fragment_x <= fragment_x + 27'b000000010000000000000000000;
//					fragment_y <= fragment_y;
//				end
//				
//				else
//				begin
//					fragment_y <= fragment_y + 27'b000000010000000000000000000;
//					fragment_x <= xMin;
//				end
//				
//				if (lambda1 > 0 & lambda2 > 0 & lambda3 > 0)
//					fragment_c <= 16'b0000000000111111;
//				else
//				//HERE WE NEED TO PASS OUT NOT TO WRITE TO SRAM
//					fragment_c <= 16'b0;
//					
//				stallOUT <= 1'b1;
//						
//				xMin <= xMin;
//				xMax <= xMax;
//			
//				yMin <= yMin;
//				yMax <= yMax;
//			end
//			
//			else
//			begin
//				//HERE WE NEED TO PASS OUT NOT TO WRITE TO SRAM
//				stallOUT <= 1'b0;
//				
//				fragment_x <= fragment_x;
//				fragment_y <= fragment_y;
//				fragment_c <= 16'b0;
//		
//				xMin <= xMin;
//				xMax <= xMax;
//		
//				yMin <= yMin;
//				yMax <= yMax;
//			end
//		end
//	end
//	
//	else if (stallOUT & stallIN)
//	begin
//		stallOUT <= stallOUT;
//		fragment_x <= fragment_x;
//		fragment_y <= fragment_y;
//		fragment_c <= fragment_c;
//		
//		xMin <= xMin;
//		xMax <= xMax;
//		
//		yMin <= yMin;
//		yMax <= yMax;
//		
//		setup_counter <= setup_counter;
//		
//		c <= c;
//		f <= f;