light_fragment.v

Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was t

module Light_Fragment(
						clk,
						reset,
						done,
						
						icolor,
						ocolor,
						
						x1,
						x2,
						x3,
						
						y1,
						y2,
						y3,
						
						z1,
						z2,
						z3,
						
						light_x,
						light_y,
						light_z,
						
						normal_x,
						normal_y,
						normal_z
					);

input clk, reset;
output wire done;

input [17:0] x1, x2, x3, y1, y2, y3, z1, z2, z3;
input [17:0] light_x, light_y, light_z;
input [17:0] normal_x, normal_y, normal_z;

input [7:0] icolor;
output wire [7:0] ocolor;

reg [1:0] state;

wire [17:0] product1;
reg [17:0] sum;
wire [17:0] sum_wire;

// assign inputs to multipliers for each state
wire [17:0]  in1a, in2a, in1b, in2b;

assign in1a = 	(state == 3'd0) ? normal_x  :
				(state == 3'd1) ? normal_y  :
				(state == 3'd2) ? normal_z  : 18'b0;

assign in1b = 	(state == 3'd0) ? light_x  :
				(state == 3'd1) ? light_y  :
				(state == 3'd2) ? light_z  : 18'b0;
				
				
fpmult m1 (product1, in1a, in1b);
fpadd  a1 (sum_wire, sum, product1);

parameter exit = 2'd3;

assign done = (state == exit);

assign ocolor = (sum[17] == 1)        ?                              8'b0 :   // < 0

				(sum[16:9] == 8'd129) ? 						     icolor : // >=1.000

				(sum[16:9] == 8'd128 & sum[8:0] >= 9'b111000000) ?   icolor :
																
				(sum[16:9] == 8'd128 & sum[8:0] >= 9'b110000000) ? {(icolor[7:5] > 3'b001) ? icolor[7:5]-3'b001 : 3'b0, // >=.750
																	 icolor[4:3],
																    (icolor[2:0] > 3'b001) ? icolor[2:0]-3'b001 : 3'b0 } :
																    
				(sum[16:9] == 8'd128 & sum[8:0] >= 9'b101000000) ? {(icolor[7:5] > 3'b010) ? icolor[7:5]-3'b010 : 3'b0,
																	(icolor[4:3] > 2'b01 ) ? icolor[4:3]-2'b01  : 2'b0,
																    (icolor[2:0] > 3'b010) ? icolor[2:0]-3'b010 : 3'b0 } : //>=.625
																
				(sum[16:9] == 8'd128 & sum[8:0] >= 9'b100000000) ? {(icolor[7:5] > 3'b011) ? icolor[7:5]-3'b011 : 3'b0,
																	(icolor[4:3] > 2'b01 ) ? icolor[4:3]-2'b01  : 2'b0,
																    (icolor[2:0] > 3'b011) ? icolor[2:0]-3'b011 : 3'b0 } :// >=.500
				
				(sum[16:9] == 8'd127 & sum[8:0] >= 9'b110000000) ? {(icolor[7:5] > 3'b100) ? icolor[7:5]-3'b100 : 3'b0,
																	(icolor[4:3] > 2'b10 ) ? icolor[4:3]-2'b10  : 2'b0,
																    (icolor[2:0] > 3'b100) ? icolor[2:0]-3'b100 : 3'b0 } :// >=.375
				
				(sum[16:9] == 8'd127 & sum[8:0] >= 9'b100000000) ? {(icolor[7:5] > 3'b101) ? icolor[7:5]-3'b101 : 3'b0,
																	(icolor[4:3] > 2'b10 ) ? icolor[4:3]-2'b10  : 2'b0,
																    (icolor[2:0] > 3'b101) ? icolor[2:0]-3'b101 : 3'b0 } : // >=.250
																   
				(sum[16:9] == 8'd126 & sum[8:0] >= 9'b100000000) ? {(icolor[7:5] > 3'b110) ? icolor[7:5]-3'b110 : 3'b0,    // >=.125 
																	 2'b0,
																    (icolor[2:0] > 3'b110) ? icolor[2:0]-3'b110 : 3'b0 } : 8'b0; //<.125

always@(posedge clk) begin
	if(reset) begin
		sum <= 18'b000000000000000000;
		state <= 2'd0;
	end
	else begin
		case(state)
			//do dot product now...
			0: begin
				sum <= sum_wire;
				state <= 2'd1;
			end
			1: begin
				sum <= sum_wire;
				state <= 2'd2;
			end
			2: begin
				sum <= sum_wire;
				state <= exit;
			end
		endcase
	end
end //always

endmodule