graphics_pipeline.map.rpt

Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was t

; Verilog Version                                              ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                 ; VHDL93             ; VHDL93             ;
; State Machine Processing                                     ; Auto               ; Auto               ;
; Safe State Machine                                           ; Off                ; Off                ;
; Extract Verilog State Machines                               ; On                 ; On                 ;
; Extract VHDL State Machines                                  ; On                 ; On                 ;
; Ignore Verilog initial constructs                            ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                   ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops               ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                      ; On                 ; On                 ;
; Parallel Synthesis                                           ; Off                ; Off                ;
; DSP Block Balancing                                          ; Auto               ; Auto               ;
; NOT Gate Push-Back                                           ; On                 ; On                 ;
; Power-Up Don't Care                                          ; On                 ; On                 ;
; Remove Redundant Logic Cells                                 ; Off                ; Off                ;
; Remove Duplicate Registers                                   ; On                 ; On                 ;
; Ignore CARRY Buffers                                         ; Off                ; Off                ;
; Ignore CASCADE Buffers                                       ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                        ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                    ; Off                ; Off                ;
; Ignore LCELL Buffers                                         ; Off                ; Off                ;
; Ignore SOFT Buffers                                          ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                               ; Off                ; Off                ;
; Optimization Technique                                       ; Balanced           ; Balanced           ;
; Carry Chain Length                                           ; 70                 ; 70                 ;
; Auto Carry Chains                                            ; On                 ; On                 ;
; Auto Open-Drain Pins                                         ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                        ; Off                ; Off                ;
; Perform gate-level register retiming                         ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax       ; On                 ; On                 ;
; Auto ROM Replacement                                         ; On                 ; On                 ;
; Auto Clock Enable Replacement                                ; On                 ; On                 ;
; Strict RAM Replacement                                       ; Off                ; Off                ;
; Allow Synchronous Control Signals                            ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                       ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                            ; Off                ; Off                ;
; Auto Resource Sharing                                        ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                           ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                           ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives            ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                           ; Off                ; Off                ;
; Synchronization Register Chain Length                        ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                   ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                         ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+
; Camera.v                         ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/Camera.v                                        ;
; calcMv.v                         ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/calcMv.v                                        ;
; Floating_Point.v                 ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/Floating_Point.v                                ;
; graphics_pipeline.v              ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/graphics_pipeline.v                             ;
; Rasterizer.v                     ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/Rasterizer.v                                    ;
; Reset_Delay.v                    ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/Reset_Delay.v                                   ;
; Transform.v                      ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/Transform.v                                     ;
; VGA_Audio_PLL.v                  ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/VGA_Audio_PLL.v                                 ;
; VGA_Controller.v                 ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/VGA_Controller.v                                ;
; VGA_Param.h                      ; yes             ; User File                    ; C:/graphics_pipeline/VGA_Param.h                                     ;
; face_rom.v                       ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/face_rom.v                                      ;
; vertex_rom.v                     ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/vertex_rom.v                                    ;
; z_buffer.v                       ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/z_buffer.v                                      ;
; calcMvNormal.v                   ; yes             ; User Verilog HDL File        ; C:/graphics_pipeline/calcMvNormal.v                                  ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/altsyncram.tdf          ;
; stratix_ram_block.inc            ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/stratix_ram_block.inc   ;
; lpm_mux.inc                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/lpm_mux.inc             ;
; lpm_decode.inc                   ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/lpm_decode.inc          ;
; aglobal80.inc                    ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/aglobal80.inc           ;
; a_rdenreg.inc                    ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/a_rdenreg.inc           ;
; altrom.inc                       ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/altrom.inc              ;