graphics_pipeline.map.rpt

来自「Implementation of GPU (Graphics Processi」· RPT 代码 · 共 415 行 · 第 1/5 页

RPT
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 76. Parameter Settings for Inferred Entity Instance: calcMv:mv1|fpmult:instg|unsigned_mult:mm|lpm_mult:Mult0
 77. Parameter Settings for Inferred Entity Instance: calcMv:mv2|fpmult:instg|unsigned_mult:mm|lpm_mult:Mult0
 78. Parameter Settings for Inferred Entity Instance: calcMv:mv3|fpmult:instg|unsigned_mult:mm|lpm_mult:Mult0
 79. Parameter Settings for Inferred Entity Instance: fpmult:fmult19|unsigned_mult:mm|lpm_mult:Mult0
 80. Parameter Settings for Inferred Entity Instance: fpmult:fmult16|unsigned_mult:mm|lpm_mult:Mult0
 81. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal2|fpmult:instff|unsigned_mult:mm|lpm_mult:Mult0
 82. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal1|fpmult:instff|unsigned_mult:mm|lpm_mult:Mult0
 83. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal3|fpmult:insti|unsigned_mult:mm|lpm_mult:Mult0
 84. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal3|fpmult:insth|unsigned_mult:mm|lpm_mult:Mult0
 85. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal3|fpmult:instg|unsigned_mult:mm|lpm_mult:Mult0
 86. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal2|fpmult:insti|unsigned_mult:mm|lpm_mult:Mult0
 87. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal2|fpmult:insth|unsigned_mult:mm|lpm_mult:Mult0
 88. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal2|fpmult:instg|unsigned_mult:mm|lpm_mult:Mult0
 89. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal1|fpmult:insti|unsigned_mult:mm|lpm_mult:Mult0
 90. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal1|fpmult:insth|unsigned_mult:mm|lpm_mult:Mult0
 91. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal1|fpmult:instg|unsigned_mult:mm|lpm_mult:Mult0
 92. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal2|fpmult:inst6|unsigned_mult:mm|lpm_mult:Mult0
 93. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal2|fpmult:inst5|unsigned_mult:mm|lpm_mult:Mult0
 94. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal2|fpmult:inst4|unsigned_mult:mm|lpm_mult:Mult0
 95. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal2|fpmult:inst3|unsigned_mult:mm|lpm_mult:Mult0
 96. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal2|fpmult:inst2|unsigned_mult:mm|lpm_mult:Mult0
 97. Parameter Settings for Inferred Entity Instance: calcMvNormal:mvnormal2|fpmult:inst1|unsigned_mult:mm|lpm_mult:Mult0
 98. lpm_mult Parameter Settings by Entity Instance
 99. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Dec 09 23:23:08 2008    ;
; Quartus II Version                 ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name                      ; graphics_pipeline                        ;
; Top-level Entity Name              ; graphics_pipeline                        ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 23,622                                   ;
;     Total combinational functions  ; 23,622                                   ;
;     Dedicated logic registers      ; 2,320                                    ;
; Total registers                    ; 2320                                     ;
; Total pins                         ; 126                                      ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 391,680                                  ;
; Embedded Multiplier 9-bit elements ; 54                                       ;
; Total PLLs                         ; 1                                        ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option                                                       ; Setting            ; Default Value      ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device                                                       ; EP2C35F672C6       ;                    ;
; Top-level entity name                                        ; graphics_pipeline  ; graphics_pipeline  ;
; Family name                                                  ; Cyclone II         ; Stratix II         ;
; Use Generated Physical Constraints File                      ; Off                ;                    ;
; Auto RAM Replacement                                         ; Off                ; On                 ;
; Auto Shift Register Replacement                              ; Off                ; Auto               ;
; Use smart compilation                                        ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation          ; 1                  ; 1                  ;
; Restructure Multiplexers                                     ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                          ; Off                ; Off                ;
; Preserve fewer node names                                    ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                    ; Off                ; Off                ;

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