⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 calcmv.v

📁 Implementation of GPU (Graphics Processing Unit) that rendered triangle based models. Our goal was t
💻 V
字号:
module calcMv 	
	(
			input clk, input reset,
			input wire [17:0] xu,	input wire [17:0] yu,	input wire [17:0] zu,
			input wire [17:0] xv,	input wire [17:0] yv,	input wire [17:0] zv,
			input wire [17:0] xw,	input wire [17:0] yw,	input wire [17:0] zw,
			input wire [17:0] xe,	input wire [17:0] ye,	input wire [17:0] ze,
			input wire [17:0]  x, 	input wire [17:0]  y, 	input wire [17:0]  z,
			output wire [17:0] Out0,
			output wire [17:0] Out1,
			output wire [17:0] Out2,
			output reg done
	);
	
	
	/* Matrix multiplication to find Mv * Vertex Matrix
	
				MV								Vertices
	[	xu	yu	zu	-xe*xu + -ye*yu + -ze*zu]		[x]
	[	xv	yv	zv	-xe*xv + -ye*yv + -ze*zv]		[y]
	[	xw	yw	zw	-xe*xw + -ye*yw + -ze*zw]		[z]
	[	0	0	0	1						]		[1]
	*/

	wire [17:0] xuw, xvw, xww, yuw, yvw, yww, zuw, zvw, zww; //w indicates wire, r indicates register
	wire [17:0] xuw_yuw, xvw_yvw, xww_yww, xuw_yuw_zuw, xvw_yvw_zvw, xww_yww_zww;
	wire [17:0] xu_x, yu_y, zu_z, xv_x, yv_y, zv_z, xw_x, yw_y, zw_z, sum0, sum1, sum2, preOut0, preOut1, preOut2;
	
	reg [17:0] xuwr, yuwr, xvwr, yvwr, xwwr, ywwr, xuw_yuw_r, xvw_yvw_r, xww_yww_r, zur, zvr, zwr;
	reg [17:0] xu_xr, yu_yr, xv_xr, yv_yr, xw_xr, yw_yr, sum0r, sum1r, sum2r, zu_zr,  zv_zr,  zw_zr;

	reg [17:0] Mvu, Mvv, Mvw, preOut0r, preOut1r, preOut2r;
	
	reg [4:0] state;
	
	/* 1st Cycle: calculate components within the matrix */
	fpmult inst1(xuw, xu, xe);	//-xe * xu		xuwr
	fpmult inst2(yuw, yu, ye);	//-ye * yu		yuwr
	fpmult inst3(zuw, zu, ze);	//-ze * zu		zuwr
	
	fpmult inst4(xvw, xv, xe);	//-xe * xv		xvwr
	fpmult inst5(yvw, yv, ye);	//-ye * yv		yvwr
	fpmult inst6(zvw, zv, ze);	//-ze * zv		zvwr
	
	fpmult inst7(xww, xw, xe);	//-xe * xw		xwwr
	fpmult inst8(yww, yw, ye);	//-ye * yw		ywwr
	fpmult inst9(zww, zw, ze);	//-ze * zw		zwr
	
	/* 2nd cycle: start adding components to determine last column */
	fpadd insta(xuw_yuw, xuwr, yuwr);				//-xe*xu + -ye*yu	xuw_yuw_r
	fpadd instb(xvw_yvw, xvwr, yvwr);				//-xe*xv + -ye*yv	xvw_yvw_r
	fpadd instc(xww_yww, xwwr, ywwr);				//-xe*xw + -ye*yw	xww_yww_r
	
	/* 3rd cycle: add z componenet to determine last column */
	fpadd instd(xuw_yuw_zuw, xuw_yuw_r, zur);	//-xe*xu + -ye*yu + -ze*zu	Mvu
	fpadd inste(xvw_yvw_zvw, xvw_yvw_r, zvr);	//-xe*xv + -ye*yv + -ze*zv	Mvv
	fpadd instf(xww_yww_zww, xww_yww_r, zwr);	//-xe*xw + -ye*yw + -ze*zw	Mvw
	
	/*1st cycle matrix multiply second matrix with vertex matrix in parallel to transform matrix*/
	fpmult instg(xu_x, xu, x);//xu*x
	fpmult insth(yu_y, yu, y);//yu*y
	fpmult insti(zu_z, zu, z);//zu*z
	
	fpmult instj(xv_x, xv, x);//xv*x
	fpmult instk(yv_y, yv, y);//yv*y
	fpmult instl(zv_z, zv, z);//zv*z

	fpmult instm(xw_x, xw, x);//xw*x
	fpmult instn(yw_y, yw, y);//yw*y
	fpmult insto(zw_z, zw, z);//zw*z
		
	/* 2nd Cycle add components together*/
	fpadd instp(sum0, xu_xr, yu_yr);//xu*x + yu*y
	fpadd instq(sum1, xv_xr, yv_yr);//xv*x + yv*y
	fpadd instr(sum2, xw_xr, yw_yr);//xw*x + yw*y

	/* 3rd Cycle add last components together*/
	fpadd instt(preOut0, sum0r, zu_zr);//xu*x + yu*y + zu*z
	fpadd instu(preOut1, sum1r, zv_zr);//xv*x + yv*y + zv*z
	fpadd instv(preOut2, sum2r, zw_zr);//xw*x + yw*y + zw*z

	/* 4th Cycle add results from each matrix together.*/
	fpadd instw(Out0, preOut0r, {~Mvu[17],Mvu[16:0]});//xu*x + yu*y + zu*z + -xe*xu + -ye*yu + -ze*zu
	fpadd instx(Out1, preOut1r, {~Mvv[17],Mvv[16:0]});//xv*x + yv*y + zv*z + -xe*xv + -ye*yv + -ze*zv
	fpadd insty(Out2, preOut2r, {~Mvw[17],Mvw[16:0]});//xw*x + yw*y + zw*z + -xe*xw + -ye*yw + -ze*zw

parameter exit = 5'd15;

	always@(posedge clk) begin
		if(reset) begin		//reset variables
			xuwr <= 18'b0;
			yuwr <= 18'b0;
			zur <= 18'b0;
			xvwr <= 18'b0;
			yvwr <= 18'b0;
			zvr <= 18'b0;
			xwwr <= 18'b0;
			ywwr <= 18'b0;
			zwr <= 18'b0;
			xu_xr <= 18'b0;
			yu_yr <= 18'b0;
			zu_zr <= 18'b0;	
			xv_xr <= 18'b0;
			yv_yr <= 18'b0;
			zv_zr <= 18'b0;
			xw_xr <= 18'b0;
			yw_yr <= 18'b0;
			zw_zr <= 18'b0;
			xuw_yuw_r <= 18'b0;
			xvw_yvw_r <= 18'b0;
			xww_yww_r <= 18'b0;
			sum0r <= 18'b0;
			sum1r <= 18'b0;
			sum2r <= 18'b0;
			Mvu <= 18'b0;
			Mvv <= 18'b0;
			Mvw <= 18'b0;
			preOut0r <= 18'b0;
			preOut1r <= 18'b0;
			preOut2r <= 18'b0;
			state <= 5'd0;
			done <= 1'b0;
		end
		else begin
			case(state)
				0: begin	//do first set of calculations and store
					//Mv calculations
					xuwr <= xuw;
					xvwr <= xvw;
					xwwr <= xww;					
					yuwr <= yuw;
					yvwr <= yvw;
					ywwr <= yww;					
					zur <= zuw;
					zvr <= zvw;
					zwr <= zww;
					//Vertex calculations
					xu_xr <= xu_x;
					yu_yr <= yu_y;
					zu_zr <= zu_z;					
					xv_xr <= xv_x;
					yv_yr <= yv_y;
					zv_zr <= zv_z;					
					xw_xr <= xw_x;
					yw_yr <= yw_y;
					zw_zr <= zw_z;					
					state <= 5'd1;
					done <= 1'b0;
				end
				1: begin	//do 2nd set of calculations and store
					//MV calcualtions
					xuw_yuw_r <= xuw_yuw;
					xvw_yvw_r <= xvw_yvw;
					xww_yww_r <= xww_yww;
					//Vertex Calculations
					sum0r <= sum0;
					sum1r <= sum1;
					sum2r <= sum2;
					state <= 5'd2;
					done <= 1'b0;
				end
				2: begin	//store next set of calculations
					Mvu <= xuw_yuw_zuw;
					Mvv <= xvw_yvw_zvw;
					Mvw <= xww_yww_zww;
					preOut0r <= preOut0;
					preOut1r <= preOut1;
					preOut2r <= preOut2;
					state <= exit;
					done <= 1'b0;
				end
				exit: begin
					done <= 1'b1;
				end
			endcase
		end
	end
endmodule
		

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -