multipliers.v

来自「Implementation of GPU (Graphics Processi」· Verilog 代码 · 共 39 行

////////////////////////////////////////////////////
////// signed mult of 3.24 format 2'comp////////////
////////////////////////////////////////////////////
//module signed_mult (out, a, b);
//	output 		[26:0]	out;
//	input 	signed	[26:0] 	a;
//	input 	signed	[26:0] 	b;
//	wire	signed	[26:0]	out;
//	wire 	signed	[53:0]	mult_out;
//	assign mult_out = a * b;
//	assign out = {mult_out[53], mult_out[50:24]};
//endmodule
//
////////////////////////////////////////////////////
////// signed mult of 8.19 format 2'comp////////////
////////////////////////////////////////////////////
//module signed_mult_8 (out, a, b);
//	output 		[26:0]	out;
//	input 	signed	[26:0] 	a;
//	input 	signed	[26:0] 	b;
//	wire	signed	[26:0]	out;
//	wire 	signed	[53:0]	mult_out;
//	assign mult_out = a * b;
//	assign out = {mult_out[53], mult_out[44:19]};
//endmodule

//////////////////////////////////////////////////
//// signed mult of 18 format 2'comp////////////
//////////////////////////////////////////////////
module signed_mult_2 (out, a, b);
	output 		[17:0]	out;
	input 	signed	[8:0] 	a;
	input 	signed	[8:0] 	b;
	wire	signed	[17:0]	out;
	wire 	signed	[17:0]	mult_out;
	assign mult_out = a * b;
	assign out = mult_out;
endmodule