rectangle_v01_00_02.vhd

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

----------------------------------------------------------------------------------
-- Company: 			SANDEEPANI - Bangalore
-- Engineer: 			PRAVEEN FELIX
-- 
-- Create Date:    	16:38:15 09/01/2008 
-- Design Name: 		Geometric Rectangle
-- Module Name:    	rectangular - Behavioral 
-- Project Name: 		Moving Geometric Objects on VGA monitor
-- Target Devices: 	XILINX Spartan 3 Starter Kit xc3s200-4ft256
-- Tool versions: 	XILINX ISE Project Navigator 9.2.04i, MENTOR GRAPHICS ModelSim SE 6.2f 
-- Description: 		Generates a geometric Rectangle
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- including VGA_GEOMETRY_PACKAGE
use WORK.MY_PACK.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rectangle_v01_00_02 is
    Port (
			pixel_row 		: in  STD_LOGIC_VECTOR (9 downto 0);			-- Display pixel row
         pixel_column 	: in  STD_LOGIC_VECTOR (9 downto 0);			-- Display pixel column
			updown			: in  STD_LOGIC_VECTOR (9 downto 0);			-- UP-DOWN Movement factor
			leftright		: in  STD_LOGIC_VECTOR (9 downto 0);			-- LEFT-RIGHT Movement factor
         rectangle 		: out  STD_LOGIC;										-- Rectangle out
			a_side			: out  STD_LOGIC_VECTOR (9 downto 0);			-- a side of rectangle frame
			b_side			: out  STD_LOGIC_VECTOR (9 downto 0);			-- b side of rectangle frame
			c_side			: out  STD_LOGIC_VECTOR (9 downto 0);			-- c side of rectangle frame
			d_side			: out  STD_LOGIC_VECTOR (9 downto 0)			-- d side of rectangle frame
			);
end rectangle_v01_00_02;

architecture Behavioral of rectangle_v01_00_02 is

	-- Internal Signal Description----------------------------------------------
	--	A Frame which can hold a rectangle is shown below with its boundaries marked
	--			 a				arow 		- Upper bar of the frame
	--		 -------- 		bcolumn	- Left bar of the frame
	--		|			|		crow		- Lower bar of the frame
	--	  b|			|d		dcolumn	- Right bar of the frame
	--		|			|
	--		 --------
	--			 c
	signal arow, bcolumn, crow, dcolumn	: STD_LOGIC_VECTOR (9 downto 0);		-- Four boundaries of the rectangle frame
	
begin


	-- Boundary calculation
	arow		<= updown;																	-- Upper bar
	bcolumn	<= leftright;																-- Left bar
	crow		<=	conv_std_logic_vector(RECTANGLE_HT-1,10) + updown;			-- Lower bar
	dcolumn	<= conv_std_logic_vector(RECTANGLE_LEN-1,10) + leftright;	-- Right bar

	-- Output
	rectangle	<= '1' when pixel_row >= arow and pixel_row <= crow and 
								pixel_column >= bcolumn and pixel_column <= dcolumn else
						'0';
	a_side <= arow;
	b_side <= bcolumn;
	c_side <= crow;
	d_side <= dcolumn;

end Behavioral;