triangle_v01_00_02.vhd

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

----------------------------------------------------------------------------------
-- Company: 			SANDEEPANI - Bangalore
-- Engineer: 			PRAVEEN FELIX
-- 
-- Create Date:    	17:44:57 09/01/2008 
-- Design Name: 		Geometric Triangle
-- Module Name:   	triangle - Behavioral 
-- Project Name: 		Moving Geometric Objects on VGA monitor
-- Target Devices: 	XILINX Spartan 3 Starter Kit xc3s200-4ft256
-- Tool versions: 	XILINX ISE Project Navigator 9.2.04i, MENTOR GRAPHICS ModelSim SE 6.2f 
-- Description: 		Generates a geometric Triangle
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- including VGA_GEOMETRY_PACKAGE
use WORK.MY_PACK.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity triangle_v01_00_02 is
    Port ( 
			pixel_row 		: in  STD_LOGIC_VECTOR (9 downto 0);			-- Display pixel row
         pixel_column 	: in  STD_LOGIC_VECTOR (9 downto 0);			-- Display pixel column
			updown			: in  STD_LOGIC_VECTOR (9 downto 0);			-- UP-DOWN Movement factor
			leftright		: in  STD_LOGIC_VECTOR (9 downto 0);			-- LEFT-RIGHT Movement factor
         triangle 		: out  STD_LOGIC;										-- Triangle out
			a_side			: out  STD_LOGIC_VECTOR (9 downto 0);			-- a side of triangle frame
			b_side			: out  STD_LOGIC_VECTOR (9 downto 0);			-- a side of triangle frame
			c_side			: out  STD_LOGIC_VECTOR (9 downto 0);			-- a side of triangle frame
			d_side			: out  STD_LOGIC_VECTOR (9 downto 0)			-- a side of triangle frame
			);
end triangle_v01_00_02;

architecture Behavioral of triangle_v01_00_02 is

	-- Internal Signal Description----------------------------------------------
	--	A Frame which can hold a triangle is shown below with its boundaries marked
	--			 a				arow 		- Upper bar of the frame
	--		 -------- 		bcolumn	- Left bar of the frame
	--		|			|		crow		- Lower bar of the frame
	--	  b|			|d		dcolumn	- Right bar of the frame
	--		|			|
	--		 --------
	--			 c
	signal arow, bcolumn, crow, dcolumn	: STD_LOGIC_VECTOR (9 downto 0);		-- Four boundaries of the triangle frame
	
	--------------------------------------------------------------------------------
	-- A triangle filter with its two sides is shown below
	--			w 			w - mid point of the triangle	
	--  		/\			x - left side of the triangle
	--   	 x/  \y 		y - right side of the triangle
	--     /    \
	--     ------
	signal w,x,y									: STD_LOGIC_VECTOR (9 downto 0);		-- Two sides of the triangle
	
begin

	-- Boundary calculation
	arow		<= updown;																-- Upper bar of the frame
	bcolumn	<= leftright;															-- Left bar of the frame
	crow		<=	conv_std_logic_vector(TRIANGLE_HT-1,10) + updown;		-- Lower bar of the frame
	dcolumn	<= conv_std_logic_vector(TRIANGLE_LEN-1,10) + leftright;	-- Right bar of the frame

	-- Triangle Filter
	w <= conv_std_logic_vector(63,10) + leftright;
	x <= w - (pixel_row - updown) when pixel_row >= updown else 
			"0000000000";																-- Left side of triangle
	y <= w + (pixel_row - updown) when pixel_row >= updown else 
			"0000000000";																-- Right side of triangle
	
	-- Output
	triangle <=	'1' when pixel_row >= arow and pixel_row <= crow 
								and pixel_column >= bcolumn and pixel_column <= dcolumn 
								and pixel_column >= x and pixel_column <= y 
								else
					'0';
	a_side <= arow;
	b_side <= bcolumn;
	c_side <= crow;
	d_side <= dcolumn;

end Behavioral;