vga_timing_gen_v01_00_00.vhd

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

----------------------------------------------------------------------------------
-- Company: 			SANDEEPANI - Bangalore
-- Engineer: 			PRAVEEN FELIX
-- 
-- Create Date:    	11:56:19 09/01/2008 
-- Design Name: 		VGA Timing Generator
-- Module Name:    	vga_timing_gen_v01_00_00 - Behavioral 
-- Project Name: 		Moving Geometric Objects on VGA monitor
-- Target Devices: 	XILINX Spartan 3 Starter Kit xc3s200-4ft256
-- Tool versions: 	XILINX ISE Project Navigator 9.2.04i, MENTOR GRAPHICS ModelSim SE 6.2f
-- Description: 		The module generates the HSync, VSync signal for the VGA port. It also
--							gives the Blank portion indication and hcount and vcount value.
--
-- Dependencies: 		hcouter_v01_00_00.xco, vcounter_v01_00_00.xco
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- including VGA_GEOMETRY_PACKAGE
use WORK.MY_PACK.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vga_timing_gen_v01_00_00 is
    Port ( 
			clk25 			: in  STD_LOGIC;									-- Input Clock of 25MHz
         rst 				: in  STD_LOGIC;									-- Reset Input
         vsync 			: out  STD_LOGIC;									-- Vertical Synchronous out
         hsync 			: out  STD_LOGIC;									-- Horizontal Synchronous out
         blank 			: out  STD_LOGIC;									-- Blank Out
			pixel_row		: out  STD_LOGIC_VECTOR(9 downto 0);		-- Display pixel row
			pixel_column	: out  STD_LOGIC_VECTOR(9 downto 0)			-- Display pixel column
			);
end vga_timing_gen_v01_00_00;

architecture Behavioral of vga_timing_gen_v01_00_00 is

	-- Component declaration of hcounter IP Core
	--	Count Range	-	0 to 799
	COMPONENT hcounter_v01_00_00 IS
	port (
		clk: IN std_logic;
		aclr: IN std_logic;
		thresh0: OUT std_logic;
		q: OUT std_logic_VECTOR(9 downto 0));
	END COMPONENT hcounter_v01_00_00;
	
	-- Component declaration of vcounter IP Core
	--	Count Range	-	0 to 520
	COMPONENT vcounter_v01_00_00 IS
	port (
		clk: IN std_logic;
		ce: IN std_logic;
		aclr: IN std_logic;
		q: OUT std_logic_VECTOR(9 downto 0));
	END COMPONENT vcounter_v01_00_00;
	
	-- Internal Signal Declaration
	signal b1								:STD_LOGIC;								-- Blank during Horizontal Back Porch
	signal b2								:STD_LOGIC;								-- Blank during Horizontal Front Porch
	signal b3								:STD_LOGIC;								-- Blank during Vertical Front Porch
	signal b4								:STD_LOGIC;								-- Blank during Vertical Back Porch
	signal ce_vcounter					:STD_LOGIC;								-- Clock Enable signal for VERTICAL_COUNT 
	signal vcount							:STD_LOGIC_VECTOR(9 downto 0);	-- vertical scan count(0-520)
	signal hcount							:STD_LOGIC_VECTOR(9 downto 0);	-- horizontal scan count(0-799)
	
begin

	-- Component Instantiation of hcounter
	-- Input Clock Trigger		- 25MHz Clock
	-- Asyn Clear Input			- Reset
	-- Threshold Output			- High when count value is 799
	-- Output Count(hcount)		- Gives the detail of the horizontal scan location
	HCOUNTER_PM: hcounter_v01_00_00
	port map(
				clk		=> clk25,
				aclr		=> rst,
				thresh0	=> ce_vcounter,
				q			=> hcount
				);
	
	-- Component Instantiation of vcounter
	-- Input Clock Trigger		- 25MHz Clock
	-- Clock Enable Input		- Threshold of HORIZONTAL_COUNT
	-- Asyn Clear Input			- Reset
	-- Output Count(vcount)		- Gives the detail of the vertical scan location	
	VCOUNTER_PM: vcounter_v01_00_00
	port map(
				clk	=> clk25,
				ce		=> ce_vcounter,
				aclr	=> rst,
				q		=> vcount
				);
				
				
	-- Combinational Logic
	b1						<= '1' when hcount <= (HLOW + HBACK_PORCH - 1) else '0';				-- Horizontal Back Porch Logic
	b2						<= '1' when hcount > (HCOUNT_HIGH - HFRONT_PORCH - 1) else '0';		-- Horizontal Front Porch Logic
	b3						<= '1' when vcount > (VCOUNT_HIGH - VFRONT_PORCH - 1) else '0';		-- Vertical Front Porch Logic
	b4						<= '1' when vcount <= (VLOW + VBACK_PORCH - 1) else '0';				-- Vertical Back Porch Logic
	
	
	-- Output Signal
   vsync 				<= '1' when vcount > (VLOW - 1) else '0';
	hsync 				<= '1' when hcount > (HLOW - 1) else '0';
	blank 				<= b1 or b2 or b3 or b4;
	
	pixel_column		<= hcount - (HLOW + HBACK_PORCH - 1) when b1 = '0' and b2 = '0' and b3 = '0' and b4 = '0' else
								"0000000000";
	pixel_row			<= vcount - (VLOW + VBACK_PORCH - 1) when b3 = '0' and b4 = '0' else
								"0000000000";
	
	
	
end Behavioral;