vga_geometry_package.vhd

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

--	Package File Template
--
--	Purpose: This package defines supplemental types, subtypes, 
--		 constants, and functions 


library IEEE;
use IEEE.STD_LOGIC_1164.all;

--  VGA SIGNAL TIMING:
--  The signal timings in Table 5-3 are derived for a 640-pixel by 480-row display using a
--  25 MHz pixel clock and 60 Hz