vga_geometry_v01_00_02.vhd

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

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-- Company: 			SANDEEPANI - Bangalore
-- Engineer: 			PRAVEEN FELIX
-- 
-- Create Date:    	12:45:58 09/01/2008 
-- Design Name: 		VGA Moving Geometry Top Module
-- Module Name:    	vga_geometry_v01_00_00 - Behavioral 
-- Project Name: 		Moving Geometric Objects on VGA monitor
-- Target Devices: 	XILINX Spartan 3 Starter Kit xc3s200-4ft256
-- Tool versions: 	XILINX ISE Project Navigator 9.2.04i, MENTOR GRAPHICS ModelSim SE 6.2f
-- Description: 		The module is the topmodule of the project
--							In this project geometric objects such as sqaure, rectangel and traingle 
--							is diplayed with an option to within the screen
--
-- Dependencies: 		clock_generator.xaw, vga_timing_gen_v01_00_00.vhd, geometric_shape_v01_00_02.vhd,
--							geo_motion_v01_00_02.vhd
--
-- Revision: 			v01_00_00 / v01_00_02
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vga_geometry_v01_00_00 is
    Port ( 
			clk50_in 	: in  STD_LOGIC;											-- Clock 50MHz input
         clk25			: in  std_logic;											-- 25MHz clock signal
			rst 			: in  STD_LOGIC;											-- Reset input
			rgb_sel		: in  STD_LOGIC_VECTOR (2 downto 0);				-- Color select signal
			shape_sel	: in  STD_LOGIC_VECTOR (1 downto 0);				-- Shape select signal
			move			: in  STD_LOGIC;											-- Move signal
         vga_hsync 	: out  STD_LOGIC;											-- HSync output
         vga_vsync 	: out  STD_LOGIC;											-- VSync output
         vga_rgb 		: out  STD_LOGIC_VECTOR (2 downto 0)				-- VGA Red/Green/Blue output
			);
end vga_geometry_v01_00_00;

architecture Behavioral of vga_geometry_v01_00_00 is

--	-- Component instantiation of clock generator module
--	-- The module generates a 25MHz clock
--	COMPONENT clock_generator
--	PORT(
--		CLKIN_IN : IN std_logic;
--		RST_IN : IN std_logic;          
--		CLKDV_OUT : OUT std_logic;
--		CLKIN_IBUFG_OUT : OUT std_logic;
--		CLK0_OUT : OUT std_logic;
--		LOCKED_OUT : OUT std_logic
--		);
--	END COMPONENT;
	
	-- Component Instantiation of VGA timing generator module
	-- The module generates the HSync and Vsync signal for the VGA port
	component vga_timing_gen_v01_00_00 is
		Port ( 
				clk25 			: in  STD_LOGIC;									
				rst 				: in  STD_LOGIC;									
				vsync 			: out  STD_LOGIC;									
				hsync 			: out  STD_LOGIC;									
				blank 			: out  STD_LOGIC;									
				pixel_row		: out  STD_LOGIC_VECTOR(9 downto 0);		
				pixel_column	: out  STD_LOGIC_VECTOR(9 downto 0)			
				);
	end component vga_timing_gen_v01_00_00;

	-- Component Instantiation of Geometric shape generator module
	--	The module generates the geometric shapes(Square/Rectangle/Triangle) for VGA display
	component geometric_shape_v01_00_02 is
    Port ( 
			pixel_row 		: in  STD_LOGIC_VECTOR (9 downto 0);
         pixel_column 	: in  STD_LOGIC_VECTOR (9 downto 0);
			shape_sel		: in  STD_LOGIC_VECTOR (1 downto 0);
			updown			: in  STD_LOGIC_VECTOR (9 downto 0);
			leftright		: in  STD_LOGIC_VECTOR (9 downto 0);
         geo_shape 		: out  STD_LOGIC;
			a_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			b_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			c_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			d_side			: out  STD_LOGIC_VECTOR (9 downto 0)
			);
	end component geometric_shape_v01_00_02;

	-- Component Instantiation of Motion creator for geometric shape module
	-- The module creates movement for geometric shapes
	component geo_motion_v01_00_02 is
	port(
			clk25			: in std_logic;
			rst			: in std_logic;
			move			: in  STD_LOGIC;
			a_side		: in  STD_LOGIC_VECTOR (9 downto 0);
			b_side		: in  STD_LOGIC_VECTOR (9 downto 0);
			c_side		: in  STD_LOGIC_VECTOR (9 downto 0);
			d_side		: in  STD_LOGIC_VECTOR (9 downto 0);
			updown		: out std_logic_VECTOR(9 downto 0);
			leftright	: out std_logic_VECTOR(9 downto 0)
			);
	end component geo_motion_v01_00_02;

	-- Internal Signal declaration
--	signal clk25			: std_logic;													-- 25MHz clock signal
	signal blank			: std_logic;													-- blank signal
	signal pixel_row		: std_logic_vector(9 downto 0);							-- hcount value
	signal pixel_column	: std_logic_vector(9 downto 0);							-- vcount value
	signal geo_shape		: std_logic;													-- Geometric shape
	signal a_side			: STD_LOGIC_VECTOR (9 downto 0);							-- a side of geometric frame
	signal b_side			: STD_LOGIC_VECTOR (9 downto 0);							-- b side of geometric frame
	signal c_side			: STD_LOGIC_VECTOR (9 downto 0);							-- c side of geometric frame
	signal d_side			: STD_LOGIC_VECTOR (9 downto 0);							-- d side of geometric frame
	signal updown			: std_logic_VECTOR(9 downto 0);							-- UP-DOWN movement factor
	signal leftright		: std_logic_VECTOR(9 downto 0);							-- LEFT-RIGHT movement factor

begin

--	-- Component Port Mapping of Clock Generator
--	--	CLKIN_IN 			- 50MHz in
--	--	RST_IN 				- reset in
--	--	CLKDV_OUT 			- 25MHz out
--	CLK_GEN: clock_generator
--	PORT MAP(
--				CLKIN_IN 			=> clk50_in,
--				RST_IN 				=> rst,      
--				CLKDV_OUT 			=> clk25
--				);

	-- Component port mapping of vga timing generator module
	--	clk25 			- 25MHz clock in
	--	rst 				- Reset input
	--	vsync 			- VSync to VGA port
	--	hsync 			- HSync to VGA port
	--	blank 			- Blank indication		
	--	hount				- hcounter value
	--	vcount			- vcounter value
	VGA_TIMING_GEN_PM: vga_timing_gen_v01_00_00
	Port Map( 
				clk25 			=> clk25,						
				rst 				=> rst,				
				vsync 			=> vga_vsync,							
				hsync 			=> vga_hsync,				
				blank 			=> blank,						
				pixel_row		=> pixel_row,	
				pixel_column	=> pixel_column
				);

	-- Component port mapping of Geometric shape generator
	--	pixel_row 		- Display Pixel row scan from timing gen
	--	pixel_column 	- Display Pixel column scan from timing gen
	--	shape_sel		- Shape Selector (square/rectangle/triangle) in
	--	updown			- UPDOWN movement factor from motion creater
	--	leftright		- LEFTRIGHT movement factor from motion creater
	--	geo_shape 		- Geometric shape out
	--	a_side			- a side of geometric frame to motion creater
	--	b_side			- b side of geometric frame to motion creater
	--	c_side			- c side of geometric frame to motion creater
	--	d_side			- d side of geometric frame to motion creater
	GEO_SHAPE_PM: geometric_shape_v01_00_02
   Port Map( 
				pixel_row 		=> pixel_row,
				pixel_column 	=> pixel_column,
				shape_sel		=> shape_sel,
				updown			=> updown,
				leftright		=> leftright,
				geo_shape 		=> geo_shape,
				a_side			=> a_side,
				b_side			=> b_side,
				c_side			=> c_side,
				d_side			=> d_side
				);
	
	-- Component portmapping of geometric motion module
	--	clk25 			- 25MHz clock in
	--	rst 				- Reset input
	-- move				- move input
	--	a_side			- a side of geometric frame from shape generator
	--	b_side			- b side of geometric frame from shape generator
	--	c_side			- c side of geometric frame from shape generator
	--	d_side			- d side of geometric frame from shape generator
	--	updown			- UPDOWN movement factor to shape generator
	--	leftright		- LEFTRIGHT movement factor to shape generator
	GEO_MOTION_PM: geo_motion_v01_00_02
	port map(
				clk25			=> clk25,
				rst			=> rst,
				move			=> move,
				a_side		=> a_side,
				b_side		=> b_side,
				c_side		=> c_side,
				d_side		=> d_side,
				updown		=> updown,
				leftright	=> leftright
				);


	-- RGB Output
	vga_rgb 	<= rgb_sel when blank = '0' and geo_shape = '1' else "000";


end Behavioral;