geometric_shape_v01_00_02.vhd

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

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-- Company: 			SANDEEPANI - Bangalore
-- Engineer: 			PRAVEEN FELIX
-- 
-- Create Date:    	15:40:24 09/01/2008 
-- Design Name: 		Geometric Generator
-- Module Name:    	geometric_shape - Behavioral 
-- Project Name: 		Moving Geometric Objects on VGA monitor
-- Target Devices: 	XILINX Spartan 3 Starter Kit xc3s200-4ft256
-- Tool versions: 	XILINX ISE Project Navigator 9.2.04i, MENTOR GRAPHICS ModelSim SE 6.2f 
-- Description: 		The module generates the geometric shape for the shape mentioned
--
-- Dependencies: 		square.vhd, rectangle.vhd, triangle.vhd
--
-- Revision: 			v01_00_00 / v01_00_02
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity geometric_shape_v01_00_02 is
    Port ( 
			pixel_row 		: in  STD_LOGIC_VECTOR (9 downto 0);			-- Display pixel row
         pixel_column 	: in  STD_LOGIC_VECTOR (9 downto 0);			-- Display pixel column
			shape_sel		: in  STD_LOGIC_VECTOR (1 downto 0);			-- Shape selector (Square/Rectangle/Triangle)
			updown			: in  STD_LOGIC_VECTOR (9 downto 0);			-- UP-DOWN movement input
			leftright		: in  STD_LOGIC_VECTOR (9 downto 0);			-- LEFT-RIGHT movement input
         geo_shape 		: out  STD_LOGIC;										-- Shape output
			a_side			: out  STD_LOGIC_VECTOR (9 downto 0);			-- a side of the geometric frame
			b_side			: out  STD_LOGIC_VECTOR (9 downto 0);			-- b side of the geometric frame
			c_side			: out  STD_LOGIC_VECTOR (9 downto 0);			-- c side of the geometric frame
			d_side			: out  STD_LOGIC_VECTOR (9 downto 0)			-- d side of the geometric frame
			);
end geometric_shape_v01_00_02;

architecture Behavioral of geometric_shape_v01_00_02 is

	-- Component instantiation of square generator
	component square_v01_00_02 is
    Port ( 
			pixel_row 		: in  STD_LOGIC_VECTOR (9 downto 0);
         pixel_column 	: in  STD_LOGIC_VECTOR (9 downto 0);
			updown			: in  STD_LOGIC_VECTOR (9 downto 0);
			leftright		: in  STD_LOGIC_VECTOR (9 downto 0);
         square 			: out  STD_LOGIC;
			a_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			b_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			c_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			d_side			: out  STD_LOGIC_VECTOR (9 downto 0)
			);
	end component square_v01_00_02;

	-- Component instantiation of rectangle generator
	component rectangle_v01_00_02 is
    Port (
			pixel_row 		: in  STD_LOGIC_VECTOR (9 downto 0);
         pixel_column 	: in  STD_LOGIC_VECTOR (9 downto 0);
			updown			: in  STD_LOGIC_VECTOR (9 downto 0);
			leftright		: in  STD_LOGIC_VECTOR (9 downto 0);
         rectangle	 	: out  STD_LOGIC;
			a_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			b_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			c_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			d_side			: out  STD_LOGIC_VECTOR (9 downto 0)
			);
	end component rectangle_v01_00_02;

	-- Component instantiation of triangle generator
	component triangle_v01_00_02 is
    Port ( 
			pixel_row 		: in  STD_LOGIC_VECTOR (9 downto 0);
         pixel_column 	: in  STD_LOGIC_VECTOR (9 downto 0);
			updown			: in  STD_LOGIC_VECTOR (9 downto 0);
			leftright		: in  STD_LOGIC_VECTOR (9 downto 0);
         triangle 		: out  STD_LOGIC;
			a_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			b_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			c_side			: out  STD_LOGIC_VECTOR (9 downto 0);
			d_side			: out  STD_LOGIC_VECTOR (9 downto 0)
			);
	end component triangle_v01_00_02;

	-- Internal signal declaration
	signal square_sig 														: STD_LOGIC;										-- Square signal
	signal rectangle_sig 													: STD_LOGIC;										-- Rectangle signal
	signal triangle_sig 														: STD_LOGIC;										-- Triangle signal
	signal a_square, b_square, c_square, d_square					: STD_LOGIC_VECTOR (9 downto 0);				-- Square Frame Boundaries
	signal a_rectangle, b_rectangle, c_rectangle, d_rectangle	: STD_LOGIC_VECTOR (9 downto 0);				-- Rectangle Frame Boundaried
	signal a_triangle, b_triangle, c_triangle, d_triangle			: STD_LOGIC_VECTOR (9 downto 0);				-- Triangle Frame boundaries

begin

	-- Component port mapping of square generator
	--	pixel_row 		- Display pixel row
	--	pixel_column 	- Display pixel column
	--	square			- Square out
	SQUARE_PM:  square_v01_00_02
   Port Map( 
				pixel_row 		=> pixel_row,
				pixel_column 	=> pixel_column,
				updown			=> updown,
				leftright		=> leftright,
				square			=> square_sig,
				a_side			=> a_square,
				b_side			=> b_square,
				c_side			=> c_square,
				d_side			=> d_square
				);

	-- Component port mapping of rectangle generator
	--	pixel_row 		- Display pixel row
	--	pixel_column 	- Display pixel column
	--	rectangle		- Rectangle out
	RECTANGLE_PM: rectangle_v01_00_02
	Port Map(
				pixel_row 		=> pixel_row,
				pixel_column 	=> pixel_column,
				updown			=> updown,
				leftright		=> leftright,
				rectangle	 	=> rectangle_sig,
				a_side			=> a_rectangle,
				b_side			=> b_rectangle,
				c_side			=> c_rectangle,
				d_side			=> d_rectangle
				);

	-- Component port mapping of triangle generator
	--	pixel_row 		- Display pixel row
	--	pixel_column 	- Display pixel column
	--	triangle			- Triangle out
	TRIANGLE_PM: triangle_v01_00_02
   Port Map( 
				pixel_row 		=> pixel_row,
				pixel_column 	=> pixel_column,
				updown			=> updown,
				leftright		=> leftright,
				triangle 		=> triangle_sig,
				a_side			=> a_triangle,
				b_side			=> b_triangle,
				c_side			=> c_triangle,
				d_side			=> d_triangle
				);

	-- Output
	geo_shape 	<= square_sig when shape_sel = "00" else
						rectangle_sig when shape_sel = "01" else
						triangle_sig when shape_sel = "10" else
						'0';
	a_side		<= a_square when shape_sel = "00" else
						a_rectangle when shape_sel = "01" else
						a_triangle when shape_sel = "10" else
						"0000000000";
	b_side		<= b_square when shape_sel = "00" else
						b_rectangle when shape_sel = "01" else
						b_triangle when shape_sel = "10" else
						"0000000000";
	c_side		<= c_square when shape_sel = "00" else
						c_rectangle when shape_sel = "01" else
						c_triangle when shape_sel = "10" else
						"0000000000";
	d_side		<= d_square when shape_sel = "00" else
						d_rectangle when shape_sel = "01" else
						d_triangle when shape_sel = "10" else
						"0000000000";
	
	
end Behavioral;