geo_motion_v01_00_02.vhd

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

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-- Company: 			SANDEEPANI - Bangalore
-- Engineer: 			PRAVEEN FELIX
-- 
-- Create Date:    	18:54:09 09/01/2008 
-- Design Name: 		Motion generator 
-- Module Name:   	geo_motion - Behavioral 
-- Project Name: 		Moving Geometric Objects on VGA monitor
-- Target Devices: 	XILINX Spartan 3 Starter Kit xc3s200-4ft256
-- Tool versions: 	XILINX ISE Project Navigator 9.2.04i, MENTOR GRAPHICS ModelSim SE 6.2f
-- Description: 		The module holds all the submodule that creates motion for the object
--
-- Dependencies: 		count_10ms_v01_00_02.xco, updown_count_v01_00_02.xco,
--							leftright_count_v01_00_02.xco, fsm_motion_v01_00_02
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity geo_motion_v01_00_02 is
	port(
			clk25			: in std_logic;											-- 25MHz Clock input
			rst			: in std_logic;											-- Reset input
			move			: in  STD_LOGIC;											-- Move signal in
			a_side		: in  STD_LOGIC_VECTOR (9 downto 0);				-- Side a of the frame of geometric object
			b_side		: in  STD_LOGIC_VECTOR (9 downto 0);				-- Side b of the frame of geometric object
			c_side		: in  STD_LOGIC_VECTOR (9 downto 0);				-- Side c of the frame of geometric object
			d_side		: in  STD_LOGIC_VECTOR (9 downto 0);				-- Side d of the frame of geometric object
			updown		: out std_logic_VECTOR(9 downto 0);					-- Up/Down count for updown counter
			leftright	: out std_logic_VECTOR(9 downto 0)					-- Up/Down count for leftright counter
			);
end geo_motion_v01_00_02;

architecture Behavioral of geo_motion_v01_00_02 is

	-- Component instantiation of 10 ms counter
	-- The module generates a threshold output every
	--	10ms which is the Clock enable for updown counter
	--	and leftright counter
	COMPONENT count_10msec_v01_00_02 IS
	port (
		clk: IN std_logic;
		aclr: IN std_logic;
		thresh0: OUT std_logic;
		q: OUT std_logic_VECTOR(17 downto 0));
	END COMPONENT count_10msec_v01_00_02;

	-- Component instantiation of up_down counter
	-- The module generates the up-down motion for the object
	COMPONENT updown_count_v01_00_02 IS
	port (
		clk: IN std_logic;
		up: IN std_logic;
		ce: IN std_logic;
		aclr: IN std_logic;
		q: OUT std_logic_VECTOR(9 downto 0));
	END COMPONENT updown_count_v01_00_02;

	-- Component instantiation of left-right counter
	-- The module generates the left-right motion for the object
	COMPONENT leftright_count_v01_00_02 IS
	port (
		clk: IN std_logic;
		up: IN std_logic;
		ce: IN std_logic;
		aclr: IN std_logic;
		q: OUT std_logic_VECTOR(9 downto 0));
	END COMPONENT leftright_count_v01_00_02;

	-- Component instantiation of FSM module for motion generation
	-- The module generates the up-down count for the updown and leftright counter
	COMPONENT fsm_motion_v01_00_02 is
    Port ( 
			clk25				: in  STD_LOGIC;
			rst				: in  STD_LOGIC;
			a_side			: in  STD_LOGIC_VECTOR (9 downto 0);
			b_side			: in  STD_LOGIC_VECTOR (9 downto 0);
			c_side			: in  STD_LOGIC_VECTOR (9 downto 0);
			d_side			: in  STD_LOGIC_VECTOR (9 downto 0);
			up_updown		: out STD_LOGIC;
			up_leftright	: out STD_LOGIC
			);
	END COMPONENT fsm_motion_v01_00_02;
	
	-- Internal Signal Declaration
	signal thresh_10ms	: STD_LOGIC;											-- Clock Enable for updown and leftright counter
	signal ce_movecount	: STD_LOGIC;											-- Clock Enable for movement counters
	signal up_updown		: STD_LOGIC;											-- Up/Down signal for updown counter
	signal up_leftright	: STD_LOGIC;											-- Left/Right signal for leftright counter

begin
	
	-- Component port mapping of 10ms counter 
	--	clk		- 25 MHz clock in
	--	aclr		- Reset in
	--	thresh0	- Clock enable for updown and leftright counter
	MSEC_PM: count_10msec_v01_00_02
	port map (
				clk		=> clk25,
				aclr		=> rst,
				thresh0	=> thresh_10ms
				);

	-- Component port mapping of updown counter
	--	clk	- 25Mhz Clock in
	--	up		- UP/DOWN signal from FSM
	--	ce		- Clock Enable signal from 10ms counter
	--	aclr	- Reset in
	--	q		- updown count
	UPDOWN_PM: updown_count_v01_00_02
	port map (
				clk	=> clk25,
				up		=> up_updown,
				ce		=> ce_movecount,
				aclr	=> rst,
				q		=> updown
				);
				
	-- Component port mapping of leftright counter
	--	clk	- 25Mhz Clock in
	--	up		- UP/DOWN signal from FSM
	--	ce		- Clock Enable signal from 10ms counter
	--	aclr	- Reset in
	--	q		- left right count
	LEFTRIGHT_PM: leftright_count_v01_00_02
	port map(
				clk	=> clk25,
				up		=> up_leftright,
				ce		=> ce_movecount,
				aclr	=> rst,
				q		=> leftright
				);
				
	-- Component port mapping of FSM
	--	clk25				- 25Mhz Clock in
	--	rst				- Reset in
	--	a_side			- a side of object frame position status
	--	b_side			- b side of object frame position status
	--	c_side			- c side of object frame position status
	--	d_side			- d side of object frame position status
	--	up_updown		- updown count
	--	up_leftright	- leftright count
	FSM_PM: fsm_motion_v01_00_02
   Port Map( 
				clk25				=> clk25,
				rst				=> rst,
				a_side			=> a_side,
				b_side			=> b_side,
				c_side			=> c_side,
				d_side			=> d_side,
				up_updown		=> up_updown,
				up_leftright	=> up_leftright
				);

	-- Clock Enable generation for movement counters
	ce_movecount <= thresh_10ms and move;

end Behavioral;