vga_geometric_ipcore.cli

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

NewProject(D:/praveenfelix05/moving_geo_xps92i_s3/pcores/vga_geometric_ipcore_v1_00_a/devl/projnav/vga_geometric_ipcore.ise)
SetProperty(Device Family, virtex5)
SetProperty(Device, xc5vfx30t)
SetProperty(Package, ff665)
SetProperty(Speed Grade, -3)
SetProperty(Top-Level Module Type, HDL)
SetProperty(Synthesis Tool, XST (VHDL/Verilog))
SetProperty(Simulator, Modelsim-SE Mixed)
SetPreference(PathType, Absolute)
AddLibrary(vga_geometric_ipcore_v1_00_a, D:/praveenfelix05/moving_geo_xps92i_s3/pcores, TRUE)
AddSource(D:/praveenfelix05/moving_geo_xps92i_s3/pcores/vga_geometric_ipcore_v1_00_a/hdl/vhdl/vga_geometric_ipcore.vhd, VHDL Module)
MoveToLibrary(D:/praveenfelix05/moving_geo_xps92i_s3/pcores/vga_geometric_ipcore_v1_00_a/hdl/vhdl/vga_geometric_ipcore.vhd, vga_geometric_ipcore_v1_00_a)
AddSource(D:/praveenfelix05/moving_geo_xps92i_s3/pcores/vga_geometric_ipcore_v1_00_a/hdl/vhdl/user_logic.vhd, VHDL Module)
MoveToLibrary(D:/praveenfelix05/moving_geo_xps92i_s3/pcores/vga_geometric_ipcore_v1_00_a/hdl/vhdl/user_logic.vhd, vga_geometric_ipcore_v1_00_a)
AddLibrary(proc_common_v2_00_a, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE)
AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd, VHDL Module)
MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd, proc_common_v2_00_a)
AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd, VHDL Module)
MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd, proc_common_v2_00_a)
AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd, VHDL Module)
MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd, proc_common_v2_00_a)
AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate128.vhd, VHDL Module)
MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate128.vhd, proc_common_v2_00_a)
AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family_support.vhd, VHDL Module)
MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family_support.vhd, proc_common_v2_00_a)
AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect_f.vhd, VHDL Module)
MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect_f.vhd, proc_common_v2_00_a)
AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_f.vhd, VHDL Module)
MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_f.vhd, proc_common_v2_00_a)
AddLibrary(plbv46_slave_single_v1_00_a, D:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE)
AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_00_a/hdl/vhdl/plb_address_decoder.vhd, VHDL Module)
MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_00_a/hdl/vhdl/plb_address_decoder.vhd, plbv46_slave_single_v1_00_a)
AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_00_a/hdl/vhdl/plb_slave_attachment.vhd, VHDL Module)
MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_00_a/hdl/vhdl/plb_slave_attachment.vhd, plbv46_slave_single_v1_00_a)
AddSource(D:/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_00_a/hdl/vhdl/plbv46_slave_single.vhd, VHDL Module)
MoveToLibrary(D:/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_00_a/hdl/vhdl/plbv46_slave_single.vhd, plbv46_slave_single_v1_00_a)
CloseProject()