vga_geometric_ipcore.restore

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

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      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_DRC_virtex5" "true" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_EnableCRC_virtex5" "true" 
      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File_virtex5" "false" 
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      "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_Init_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_M0_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_M1_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_M2_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Pgm_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_PwrDown_Safe_Temp_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgCfg_Rate_virtex5" "2" 
      "A" "" "" "" "PROP_xilxBitgCfg_Rdwr_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Retain_Config_Status_Register_Values_virtex5" "true" 
      "A" "" "" "" "PROP_xilxBitgCfg_SelectMAP_Abort_Sequence_virtex5" "Enable" 
      "A" "" "" "" "PROP_xilxBitgCfg_TCK_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_TDI_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_TDO_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_TMS_virtex5" "Pull Up" 
      "A" "" "" "" "PROP_xilxBitgCfg_Unused_virtex5" "Pull Down" 
      "A" "" "" "" "PROP_xilxBitgReadBk_Sec_virtex5" "Enable Readback and Reconfiguration" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_Done_virtex5" "Default (4)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut_virtex5" "Default (5)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_MatchCycle_virtex5" "Auto" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL_virtex5" "Default (NoWait)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn_virtex5" "Default (6)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_virtex5" "CCLK" 
      "A" "" "" "" "PROP_xilxBitgStart_IntDone_virtex5" "false" 
      "A" "" "" "" "PROP_xilxMapAllowLogicOpt_virtex5" "false" 
      "A" "" "" "" "PROP_xilxMapCoverMode_virtex5" "Area" 
      "A" "" "" "" "PROP_xilxMapDisableRegOrdering_virtex5" "false" 
      "A" "" "" "" "PROP_xilxMapGenInputK_virtex5" "6" 
      "A" "" "" "" "PROP_xilxMapMaxCompression_virtex5" "false" 
      "A" "" "" "" "PROP_xilxMapPackRegInto_virtex5" "Off" 
      "A" "" "" "" "PROP_xilxMapReplicateLogic_virtex5" "true" 
      "A" "" "" "" "PROP_xilxMapReportDetail_virtex5" "false" 
      "A" "" "" "" "PROP_xilxMapSliceLogicInUnusedBRAMs_virtex5" "false" 
      "A" "" "" "" "PROP_xilxMapTrimUnconnSig_virtex5" "true" 
      "A" "" "" "" "PROP_xilxNgdbldIOPads_virtex5" "false" 
      "A" "" "" "" "PROP_xilxNgdbldMacro" "" 
      "A" "" "" "" "PROP_xilxNgdbldNTType_virtex5" "Timestamp" 
      "A" "" "" "" "PROP_xilxNgdbldPresHierarchy_virtex5" "false" 
      "A" "" "" "" "PROP_xilxNgdbldUR_virtex5" "" 
      "A" "" "" "" "PROP_xilxNgdbldUnexpBlks_virtex5" "false" 
      "A" "" "" "" "PROP_xilxNgdbld_AUL" "false" 
      "A" "" "" "" "PROP_xilxPARplacerCostTable_virtex5" "1" 
      "A" "" "" "" "PROP_xilxPARstrat_virtex5" "Route Only" 
      "A" "" "" "" "PROP_xilxPARuseBondedIO_virtex5" "false" 
      "A" "" "" "" "PROP_xilxPostTrceAdvAna_virtex5" "false" 
      "A" "" "" "" "PROP_xilxPostTrceRptLimit_virtex5" "3" 
      "A" "" "" "" "PROP_xilxPostTrceRpt_virtex5" "Error Report" 
      "A" "" "" "" "PROP_xilxPostTrceStamp_virtex5" "" 
      "A" "" "" "" "PROP_xilxPostTrceTSIFile_virtex5" "" 
      "A" "" "" "" "PROP_xilxPostTrceUncovPath_virtex5" "" 
      "A" "" "" "" "PROP_xilxPreTrceAdvAna_virtex5" "false" 
      "A" "" "" "" "PROP_xilxPreTrceRptLimit_virtex5" "3" 
      "A" "" "" "" "PROP_xilxPreTrceRpt_virtex5" "Error Report" 
      "A" "" "" "" "PROP_xilxPreTrceUncovPath_virtex5" "" 
      "A" "" "" "" "PROP_xilxSynthAddIObuf" "true" 
      "A" "" "" "" "PROP_xilxSynthGlobOpt_virtex5" "AllClockNets" 
      "A" "" "" "" "PROP_xilxSynthKeepHierarchy" "No" 
      "A" "" "" "" "PROP_xilxSynthKeepHierarchy_CPLD" "Yes" 
      "A" "" "" "" "PROP_xilxSynthMacroPreserve" "true" 
      "A" "" "" "" "PROP_xilxSynthRegBalancing_virtex5" "No" 
      "A" "" "" "" "PROP_xilxSynthRegDuplication_virtex5" "true" 
      "A" "" "" "" "PROP_xilxSynthXORPreserve" "true" 
      "A" "" "" "" "PROP_xstAsynToSync_virtex5" "false" 
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      "A" "" "" "" "PROP_xstBusDelimiter" "<>" 
      "A" "" "" "" "PROP_xstCase" "Maintain" 
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      "A" "" "" "" "PROP_xstGenerateRTLNetlist" "Yes" 
      "A" "" "" "" "PROP_xstGenericsParameters" "" 
      "A" "" "" "" "PROP_xstHierarchySeparator" "/" 
      "A" "" "" "" "PROP_xstIniFile" "" 
      "A" "" "" "" "PROP_xstLibSearchOrder" "" 
      "A" "" "" "" "PROP_xstOptimizeInsPrimtives_virtex5" "false" 
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      "A" "" "" "" "PROP_xstPowerOptimization_virtex5" "false" 
      "A" "" "" "" "PROP_xstReadCores_virtex5" "true" 
      "A" "" "" "" "PROP_xstSlicePacking_virtex5" "true" 
      "A" "" "" "" "PROP_xstSliceUtilRatio_virtex5" "100" 
      "A" "" "" "" "PROP_xstUseClockEnable_virtex5" "Auto" 
      "A" "" "" "" "PROP_xstUseSyncReset_virtex5" "Auto" 
      "A" "" "" "" "PROP_xstUseSyncSet_virtex5" "Auto" 
      "A" "" "" "" "PROP_xstUseSynthConstFile" "true" 
      "A" "" "" "" "PROP_xstUserCompileList" "" 
      "A" "" "" "" "PROP_xstVeriIncludeDir_Global" "" 
      "A" "" "" "" "PROP_xstVerilog2001" "true" 
      "A" "" "" "" "PROP_xstVerilogMacros" "" 
      "A" "" "" "" "PROP_xstWorkDir" "./xst" 
      "A" "" "" "" "PROP_xstWriteTimingConstraints_virtex5" "false" 
      "A" "" "" "" "PROP_xst_otherCmdLineOptions" "" 
      "A" "AutoGeneratedView" "VIEW_AbstractSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_AnalyzedDesign" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_AnnotatedResultsModelSim" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_BehavioralSimulationModelSim" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_FPGAConfiguration" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_FPGAConfigureDevice" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_FPGAGeneratePROM" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Map" "" "PROP_SmartGuide" "false" 
      "A" "AutoGeneratedView" "VIEW_Map" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Par" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-MapPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-MapSimulationModelSim" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-ParSimulationModelSim" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-SynthesisAbstractSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-TranslatePreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-TranslateSimulationModelSim" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_PostAbstractSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_TopDesignUnit" "" 
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      "A" "AutoGeneratedView" "VIEW_TBWBehavioralSimulationModelSim" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_TBWPost-MapSimulationModelSim" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_TBWPost-ParSimulationModelSim" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_TopDesignUnit" "" 
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      "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SmartGuide" "false" 
      "A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_TopDesignUnit" "" 
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      "A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_SmartGuide" "false" 
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      "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_xstVeriIncludeDir" "" 
      "A" "VIEW_Initial" "VIEW_Initial" "" "PROP_TopDesignUnit" "" 
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      "B" "" "" "" "PROP_ModelSimProcWin" "false" 
      "B" "" "" "" "PROP_ModelSimSignalWin" "true" 
      "B" "" "" "" "PROP_ModelSimSimRes" "Default (1 ps)" 
      "B" "" "" "" "PROP_ModelSimSimRunTime_tb" "1000ns" 
      "B" "" "" "" "PROP_ModelSimSimRunTime_tbw" "1000ns" 
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      "B" "" "" "" "PROP_ModelSimUutInstName_postMap" "UUT" 
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      "B" "" "" "" "PROP_SimCustom_postPar" "" 
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      "B" "" "" "" "PROP_SimGenVcdFile" "false" 
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      "B" "" "" "" "PROP_Simulator" "Modelsim-XE VHDL" 
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      "B" "" "" "" "PROP_XPowerOptMaxNumberLines" "1000" 
      "B" "" "" "" "PROP_XPowerOptUseTimeBased" "false" 
      "B" "" "" "" "PROP_bitgen_Encrypt_Encrypt_virtex5" "false" 
      "B" "" "" "" "PROP_impactBaud" "None" 
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      "B" "" "" "" "PROP_parMpprNodelistFile_virtex5" "" 
      "B" "" "" "" "PROP_parMpprParIterations_virtex5" "3" 
      "B" "" "" "" "PROP_parMpprResultsDirectory_virtex5" "" 
      "B" "" "" "" "PROP_parMpprResultsToSave_virtex5" "" 
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      "B" "" "" "" "PROP_vlog_otherCmdLineOptions" "" 
      "B" "" "" "" "PROP_vsim_otherCmdLineOptions" "" 
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      "B" "" "" "" "PROP_xilxBitgCfg_BPI_First_Read_Cycle_virtex5" "2" 
      "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr_virtex5" "false" 
      "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex5" "false" 
      "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile_virtex5" "false" 
      "B" "" "" "" "PROP_xilxBitgReadBk_GenBitStr_virtex5" "false" 
      "B" "" "" "" "PROP_xilxPAReffortLevel_virtex5" "Standard" 
      "B" "" "" "" "PROP_xstMoveFirstFfStage_virtex5" "true" 
      "B" "" "" "" "PROP_xstMoveLastFfStage_virtex5" "true" 
      "B" "" "" "" "PROP_xstROMStyle_virtex5" "Auto" 
      "B" "" "" "" "PROP_xstSafeImplement" "No" 
      "B" "AutoGeneratedView" "VIEW_Map" "" "PROP_ParSmartGuideFileName" "" 
      "B" "AutoGeneratedView" "VIEW_Translation" "" "PROP_MapSmartGuideFileName" "" 
      "C" "" "" "" "PROP_AceActiveName_virtex5" "" 
      "C" "" "" "" "PROP_CompxlibLang" "VHDL" 
      "C" "" "" "" "PROP_CompxlibSimPath" "C:/Modeltech_6.2f/win32" 
      "C" "" "" "" "PROP_DevDevice" "xc5vlx20t" 
      "C" "" "" "" "PROP_DevFamilyPMName" "virtex5" 
      "C" "" "" "" "PROP_SimModelGenMultiHierFile" "false" 
      "C" "" "" "" "PROP_XPowerOptBaseTimeUnit" "ps" 
      "C" "" "" "" "PROP_XPowerOptNumberOfUnits" "1" 
      "C" "" "" "" "PROP_bitgen_Encrypt_key0_virtex5" "" 
      "C" "" "" "" "PROP_bitgen_Encrypt_keyFile_virtex5" "" 
      "C" "" "" "" "PROP_impactConfigFileName_virtex5" "" 
      "C" "" "" "" "PROP_xilxBitgCfg_Fallback_Reconfig_virtex5" "Enable" 
      "C" "" "" "" "PROP_xilxPARextraEffortLevel_virtex5" "None" 
      "D" "" "" "" "PROP_CompxlibUni9000Lib" "true" 
      "D" "" "" "" "PROP_CompxlibUniSimLib" "true" 
      "D" "" "" "" "PROP_CompxlibUniSimLib_virtex5" "false" 
      "D" "" "" "" "PROP_DevPackage" "ff323" 
      "D" "" "" "" "PROP_Synthesis_Tool" "XST (VHDL/Verilog)" 
      "E" "" "" "" "PROP_DevSpeed" "-3" 
      "E" "" "" "" "PROP_PreferredLanguage" "VHDL" 
      "F" "" "" "" "PROP_ChangeDevSpeed" "-3" 
      "F" "" "" "" "PROP_SimModelTarget" "VHDL" 
      "F" "" "" "" "PROP_tbwTestbenchTargetLang" "VHDL" 
      "F" "" "" "" "PROP_xilxPostTrceSpeed_virtex5" "-3" 
      "F" "" "" "" "PROP_xilxPreTrceSpeed_virtex5" "-3" 
      "G" "" "" "" "PROP_PostSynthSimModelName" "_synthesis.vhd" 
      "G" "" "" "" "PROP_SimModelAutoInsertGlblModuleInNetlist" "true" 
      "G" "" "" "" "PROP_SimModelGenArchOnly" "false" 
      "G" "" "" "" "PROP_SimModelIncSdfAnnInVerilogFile" "true" 
      "G" "" "" "" "PROP_SimModelIncSimprimInVerilogFile" "false" 
      "G" "" "" "" "PROP_SimModelIncUnisimInVerilogFile" "false" 
      "G" "" "" "" "PROP_SimModelIncUselibDirInVerilogFile" "false" 
      "G" "" "" "" "PROP_SimModelNoEscapeSignal" "false" 
      "G" "" "" "" "PROP_SimModelOutputExtIdent" "false" 
      "G" "" "" "" "PROP_SimModelRenTopLevArchTo" "Structure" 
      "G" "" "" "" "PROP_SimModelRenTopLevMod" "" 
      "G" "AutoGeneratedView" "VIEW_Map" "" "PROP_PostMapSimModelName" "_map.vhd" 
      "G" "AutoGeneratedView" "VIEW_Par" "" "PROP_PostParSimModelName" "_timesim.vhd" 
      "G" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_tbwPostMapTestbenchName" "" 
      "G" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_tbwPostParTestbenchName" "" 
      "G" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_tbwPostXlateTestbenchName" "" 
      "G" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_tbwPostMapTestbenchName" "" 
      "G" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_tbwPostParTestbenchName" "" 
      "G" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_tbwPostXlateTestbenchName" "" 
      "G" "AutoGeneratedView" "VIEW_Translation" "" "PROP_PostXlateSimModelName" "_translate.vhd" 
      "H" "" "" "" "PROP_SimModelBringOutGsrNetAsAPort" "false" 
      "H" "" "" "" "PROP_SimModelBringOutGtsNetAsAPort" "false" 
      "H" "" "" "" "PROP_SimModelPathUsedInSdfAnn" "Default" 
      "H" "AutoGeneratedView" "VIEW_Map" "" "PROP_SimModelRenTopLevEntTo" "" 
      "H" "AutoGeneratedView" "VIEW_Par" "" "PROP_SimModelRenTopLevEntTo" "" 
      "H" "AutoGeneratedView" "VIEW_Structural" "" "PROP_SimModelRenTopLevEntTo" "" 
      "H" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SimModelRenTopLevEntTo" "" 
      "I" "" "" "" "PROP_SimModelGsrPortName" "GSR_PORT" 
      "I" "" "" "" "PROP_SimModelGtsPortName" "GTS_PORT" 
      "I" "" "" "" "PROP_SimModelRocPulseWidth" "100" 
      "I" "" "" "" "PROP_SimModelTocPulseWidth" "0"}

  HandleException {
    RestoreProcessProperties $iProjHelper $process_props
  } "A problem occured while restoring process properties."

   # library names and their members
   set libraries {
   }

  HandleException {
    RestoreSourceLibraries $iProjHelper $libraries
  } "A problem occured while restoring source libraries."

   # Close the facilitator project.
   CloseFacilProject $iProjHelper

   # Open the restored project in the user's client application,
   # which will either be the Projnav GUI or xtclsh.
   project open $project_file

   # Let the user know about the backed up project file.
   INFO "The project \"$project_file\" was successfully recovered and opened."
   if {$wasBackedUp} {
      INFO ""
      INFO "The original project was renamed as \"$backup_file\"."
      INFO "Please open a Technical Support WebCase at"
      INFO "www.xilinx.com/support/clearexpress/websupport.htm"
      INFO "and submit this file, along with the project source files, for evaluation."
   }
}