xparameters.h

Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the process

#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_1               0x820007FF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_1                 0xCE000000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_1 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_1               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_1              1
#define XPAR_OPB_PCI_1_IPIFBAR_2                     0x82320000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_2               0x8232FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_2                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_2 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_2               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_2              1
#define XPAR_OPB_PCI_1_IPIFBAR_3                     0x82330000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_3               0x8233FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_3                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_3 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_3               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_3              0
#define XPAR_OPB_PCI_1_IPIFBAR_4                     0x82340000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_4               0x8234FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_4                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_4 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_4               0
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_4              0
#define XPAR_OPB_PCI_1_IPIFBAR_5                     0x82350000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_5               0x8235FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_5                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_5 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_5               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_5              1
#define XPAR_OPB_PCI_1_DMA_BASEADDR                  0x87000000
#define XPAR_OPB_PCI_1_DMA_HIGHADDR                  0x8700007F
#define XPAR_OPB_PCI_1_DMA_CHAN_TYPE                 0
#define XPAR_OPB_PCI_1_DMA_LENGTH_WIDTH              11

/*****************************************************************************
 *
 * GEmac defines.
 * DeviceID starts at 210
 */
#define XPAR_XGEMAC_NUM_INSTANCES    1
#define XPAR_GEMAC_0_DEVICE_ID       210
#define XPAR_GEMAC_0_BASEADDR        0x61000000
#define XPAR_GEMAC_0_DMA_TYPE        9
#define XPAR_GEMAC_0_MIIM_EXIST      0
#define XPAR_GEMAC_0_INCLUDE_STATS   0


/*****************************************************************************
 *
 * Touchscreen defines .
 * DeviceID starts at 220
 */
#define XPAR_XTOUCHSCREEN_NUM_INSTANCES  1
#define XPAR_TOUCHSCREEN_0_DEVICE_ID     220
#define XPAR_TOUCHSCREEN_0_BASEADDR      0x70000000


/*****************************************************************************
 *
 * DDR defines .
 * DeviceID starts at 230
 */
#define XPAR_XDDR_NUM_INSTANCES         1
#define XPAR_DDR_0_DEVICE_ID            230
#define XPAR_DDR_0_BASEADDR             0
#define XPAR_DDR_0_INTERRUPT_PRESENT    0

/*****************************************************************************
 *
 * EmacLite defines .
 * DeviceID starts at 240
 */
#define XPAR_XEMACLITE_NUM_INSTANCES    1
#define XPAR_EMACLITE_0_DEVICE_ID       240
#define XPAR_EMACLITE_0_BASEADDR        0
#define XPAR_EMACLITE_0_TX_PING_PONG    0
#define XPAR_EMACLITE_0_RX_PING_PONG    0

/*****************************************************************************
 *
 * DSDAC defines .
 * DeviceID starts at 250
 */
#define XPAR_XDSDAC_NUM_INSTANCES       1
#define XPAR_DSDAC_0_DEVICE_ID          250
#define XPAR_DSDAC_0_BASEADDR           0

/*****************************************************************************
 *
 * DSADC defines .
 * DeviceID starts at 260
 */
#define XPAR_XDSADC_NUM_INSTANCES       1
#define XPAR_DSADC_0_DEVICE_ID          260
#define XPAR_DSADC_0_BASEADDR           0

/*****************************************************************************
 *
 * PCI Arbiter defines.
 * DeviceID starts at 270
 */
#define XPAR_XPCIARB_NUM_INSTANCES     1
#define XPAR_OPB_PCI_ARBITER_0_DEVICE_ID     270
#define XPAR_OPB_PCI_ARBITER_0_BASEADDR      0
#define XPAR_OPB_PCI_ARBITER_0_NUM_PCI_MSTRS 2

/*****************************************************************************
 *
 * TEMAC defines .
 * DeviceID starts at 280
 */
#define XPAR_XTEMAC_NUM_INSTANCES       1
#define XPAR_TEMAC_0_DEVICE_ID          280
#define XPAR_TEMAC_0_BASEADDR           0
#define XPAR_TEMAC_0_DMA_TYPE        3
#define XPAR_TEMAC_0_RDFIFO_DEPTH    131072
#define XPAR_TEMAC_0_WRFIFO_DEPTH    131072
#define XPAR_TEMAC_0_MAC_FIFO_DEPTH  16
#define XPAR_TEMAC_0_TEMAC_DCR_HOST  0
#define XPAR_TEMAC_0_DRE             0

/*****************************************************************************
 *
 * DMACENTRAL defines .
 * DeviceID starts at 290
 */
#define XPAR_XDMACENTRAL_NUM_INSTANCES       1
#define XPAR_DMACENTRAL_0_DEVICE_ID          290
#define XPAR_DMACENTRAL_0_BASEADDR           0
#define XPAR_DMACENTRAL_0_READ_OPTIONAL_REGS 0

/*****************************************************************************
 *
 * CAN defines
 * DeviceID starts at 300
 */
#define XPAR_XCAN_NUM_INSTANCES  1
#define XPAR_CAN_0_DEVICE_ID     300

/******************************************************************
 * Embedded Processor Block (EPB) Defines
 * Also known as Angelfire.
 */

/* Definitions for driver UARTEPB */
#define XPAR_XUARTEPB_NUM_INSTANCES 2

/* Definitions for peripheral EPB_0 - EPB_UART1 */
#define XPAR_EPB_0_UART1_BASEADDR 0x7D802000
#define XPAR_EPB_0_UART1_DEVICE_ID 0
#define XPAR_EPB_0_UART1_CLOCK_HZ 66666666

/* Definitions for peripheral EPB_0 - EPB_UART2 */
#define XPAR_EPB_0_UART2_BASEADDR 0x7D803000
#define XPAR_EPB_0_UART2_DEVICE_ID 1
#define XPAR_EPB_0_UART2_CLOCK_HZ 66666666


/******************************************************************/

/* Definitions for driver SPIEPB */
#define XPAR_XSPIEPB_NUM_INSTANCES 2

/* Definitions for peripheral EPB_0 - EPB_SPI1 */
#define XPAR_EPB_0_SPI1_BASEADDR 0x7D804000
#define XPAR_EPB_0_SPI1_DEVICE_ID 0
#define XPAR_EPB_0_SPI1_CLOCK_HZ 66666666

/* Definitions for peripheral EPB_0 - EPB_SPI2 */
#define XPAR_EPB_0_SPI2_BASEADDR 0x7D805000
#define XPAR_EPB_0_SPI2_DEVICE_ID 1
#define XPAR_EPB_0_SPI2_CLOCK_HZ 66666666


/******************************************************************/

/* Definitions for driver CANEPB */
#define XPAR_XCANEPB_NUM_INSTANCES 2

/* Definitions for peripheral EPB_0 - EPB_CAN1 */
#define XPAR_EPB_0_CAN1_BASEADDR 0x7D808000
#define XPAR_EPB_0_CAN1_DEVICE_ID 0

/* Definitions for peripheral EPB_0 - EPB_CAN2 */
#define XPAR_EPB_0_CAN2_BASEADDR 0x7D809000
#define XPAR_EPB_0_CAN2_DEVICE_ID 1


/******************************************************************/

/* Definitions for driver INTCEPB */
#define XPAR_XINTCEPB_NUM_INSTANCES 1

/* Definitions for peripheral EPB_0 - EPB_INTC */
#define XPAR_EPB_0_INTC_BASEADDR 0x7D80C000
#define XPAR_EPB_0_INTC_DEVICE_ID 0
#define XPAR_EPB_0_INTC_KIND_OF_INTR 0x00000000

/* Interrupt Identifiers for EPB_0_INTC */
#define XPAR_EPB_0_EMAC_INTR   2
#define XPAR_EPB_0_USB_INTR    3
#define XPAR_EPB_0_UART1_INTR  4
#define XPAR_EPB_0_UART2_INTR  5
#define XPAR_EPB_0_SPI1_INTR   6
#define XPAR_EPB_0_SPI2_INTR   7
#define XPAR_EPB_0_I2C1_INTR   8
#define XPAR_EPB_0_I2C2_INTR   9
#define XPAR_EPB_0_CAN1_INTR   10
#define XPAR_EPB_0_CAN2_INTR   11
#define XPAR_EPB_0_WDOG_INTR   12
#define XPAR_EPB_0_TTC1_INTR   13
#define XPAR_EPB_0_TTC2_INTR   14
#define XPAR_EPB_0_TTC3_INTR   15


/******************************************************************/

/* Definitions for driver I2CEPB */
#define XPAR_XI2CEPB_NUM_INSTANCES 2

/* Definitions for peripheral EPB_0 - EPB_I2C1 */
#define XPAR_EPB_0_I2C1_BASEADDR 0x7D806000
#define XPAR_EPB_0_I2C1_DEVICE_ID 0
#define XPAR_EPB_0_I2C1_CLOCK_HZ 66666666

/* Definitions for peripheral EPB_0 - EPB_I2C2 */
#define XPAR_EPB_0_I2C2_BASEADDR 0x7D807000
#define XPAR_EPB_0_I2C2_DEVICE_ID 1
#define XPAR_EPB_0_I2C2_CLOCK_HZ 66666666


/******************************************************************/

/* Definitions for driver TTCEPB */
#define XPAR_XTTCEPB_NUM_INSTANCES 3

/* Definitions for peripheral EPB_0 - EPB_TTC1 */
#define XPAR_EPB_0_TTC1_BASEADDR 0x7D80B000
#define XPAR_EPB_0_TTC1_DEVICE_ID 0
#define XPAR_EPB_0_TTC1_CLOCK_HZ 66666666

/* Definitions for peripheral EPB_0 - EPB_TTC2 */
#define XPAR_EPB_0_TTC2_BASEADDR 0x7D80B004
#define XPAR_EPB_0_TTC2_DEVICE_ID 1
#define XPAR_EPB_0_TTC2_CLOCK_HZ 66666666

/* Definitions for peripheral EPB_0 - EPB_TTC3 */
#define XPAR_EPB_0_TTC3_BASEADDR 0x7D80B008
#define XPAR_EPB_0_TTC3_DEVICE_ID 2
#define XPAR_EPB_0_TTC3_CLOCK_HZ 66666666


/******************************************************************/

/* Definitions for driver WDTEPB */
#define XPAR_XWDTEPB_NUM_INSTANCES 1

/* Definitions for peripheral EPB_0 - EPB_WDT */
#define XPAR_EPB_0_WDT_BASEADDR 0x7D80A000
#define XPAR_EPB_0_WDT_DEVICE_ID 0


/******************************************************************/

/* Definitions for driver EMACEPB */
#define XPAR_XEMACEPB_NUM_INSTANCES 1

/* Definitions for peripheral EPB_0 - EPB_EMAC */
#define XPAR_EPB_0_EMAC_BASEADDR 0x7D800000
#define XPAR_EPB_0_EMAC_DEVICE_ID 0


/******************************************************************/

/* Definitions for driver USBEPB */
#define XPAR_XUSBEPB_NUM_INSTANCES 1

/* Definitions for peripheral EPB_0 - EPB_USB */
#define XPAR_EPB_0_USB_BASEADDR 0x7D801000
#define XPAR_EPB_0_USB_DEVICE_ID 0


/******************************************************************/

/* Definitions for driver ADCEPB */
#define XPAR_XADCEPB_NUM_INSTANCES 1

/* Definitions for peripheral EPB_0 - EPB_ADC */
#define XPAR_EPB_0_ADC_BASEADDR 0x7D80D000
#define XPAR_EPB_0_ADC_DEVICE_ID 0
#define XPAR_EPB_0_ADC_CLOCK_HZ 66666666

/* Definitions for FLEXRAY Driver */
#define XPAR_XFLEXRAY_NUM_INSTANCES 1
#define XPAR_OPB_FLEXRAY_0_DEVICE_ID    0
#define XPAR_OPB_FLEXRAY_0_BASEADDR  0x7D80E000
#define XPAR_OPB_FLEXRAY_MAX_PAYLOAD_SIZE 254
#define XPAR_OPB_FLEXRAY_NO_OF_TX_BUFFERS   128
#define XPAR_OPB_FLEXRAY_NO_OF_RX_BUFFERS   128
#define XPAR_OPB_FLEXRAY_RX_FIFO_DEPTH      16

/* Definitions for MOST driver */
#define XPAR_XMOST_NUM_INSTANCES 1
#define XPAR_OPB_MOST_0_DEVICE_ID 0
#define XPAR_OPB_MOST_0_BASEADDR 0x7D810000
#define XPAR_OPB_MOST_OPMODE	0
#define XPAR_OPB_MOST_FWC 16
#define XPAR_OPB_MOST_EWC 16

/* Definitions for USB driver */
#define XPAR_XUSB_NUM_INSTANCES	1
#define XPAR_USB_0_DEVICE_ID	0
#define XPAR_USB_0_BASEADDR	0x7D813000

/*****************************************************************************
 *
 * HWICAP defines .
 */
#define XPAR_XHWICAP_NUM_INSTANCES       1
#define XPAR_OPB_HWICAP_0_DEVICE_ID      0
#define XPAR_OPB_HWICAP_0_BASEADDR        0xFFFFFFFF

/*****************************************************************************
 *
 * LLTEMAC and LLFIFO defines .
 */
#define XPAR_XLLTEMAC_NUM_INSTANCES      1
#define XPAR_XLLFIFO_NUM_INSTANCES       1

/*****************************************************************************
 *
 * PCIe defines .
 */
#define XPAR_XPCIE_NUM_INSTANCES       1

/*****************************************************************************
 *
 * MPMC defines .
 */
#define XPAR_XMPMC_NUM_INSTANCES         1

/*****************************************************************************
 *
 * SYSMON defines .
 */
#define XPAR_XSYSMON_NUM_INSTANCES         1


/*****************************************************************************
 *
 * SYSMON defines .
 */
#define XPAR_XSYSMON_NUM_INSTANCES         1

/*****************************************************************************
 *
 * MBox defines .
 */
#define XPAR_XMBOX_NUM_INSTANCES         	1
#define XPAR_XMBOX_0_DEVICE_ID				0
#define XPAR_XMBOX_0_BASEADDR				0x7D814000
#define XPAR_XMBOX_0_NUM_CHANNELS			1
#define XPAR_XMBOX_0_USE_FSL				0


/*****************************************************************************
 *
 * Mutex defines .
 */
#define XPAR_XMUTEX_NUM_INSTANCES         	1
#define XPAR_XMUTEX_0_DEVICE_ID				0
#define XPAR_XMUTEX_0_BASEADDR				0x7D815000
#define XPAR_XMUTEX_0_NUM_MUTEX				2
#define XPAR_XMUTEX_0_ENABLE_USER			1

/*
 * MicroBlaze sets this define but for the build check to
 * function it needs to be set here
 */
#define XPAR_CPU_ID 0


/**************************** Type Definitions *******************************/


/***************** Macros (Inline Functions) Definitions *********************/

#ifdef __cplusplus
}
#endif

#endif              /* end of protection macro */