led.v

来自「此源码可以在EASYFPGA是实现跑马灯程序」· Verilog 代码 · 共 41 行

// led.v
module  led(
            clk_48M,
            reset,
            LedOut
            );
input       	clk_48M;
input       	reset;
output  [3:0]   LedOut;
reg     [20:0]  Count;
reg     [3:0]   led_reg;

wire            led_clk;

assign  led_clk=Count[20];


always@(posedge clk_48M or negedge reset)
begin
    if(!reset)
        Count<=21'd0;
    else
        Count<=Count+21'd1;
end

always@(posedge led_clk or negedge reset)
begin
    if(!reset)
        led_reg<=4'd0;
    else
    begin
        if(led_reg==4'd0)
            led_reg<=4'd1;
        else
            led_reg<=led_reg<<1'b1;
    end
end

assign LedOut=led_reg;

endmodule