csc.v

color space convert verilog

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 		 SJTU
// Engineer:		 Que Youlin
//
// Create Date:    15:57:31 11/29/06
// Design Name:    
// Module Name:    csc
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module csc(Clock, Reset, X, Y, Z, R, G, B);

  parameter OUT_SIZE  =  12; // uncomment to get  12-bit input & output...


  input  Clock; 
  input  Reset;
  input  [(OUT_SIZE - 1):0] X; 
  input  [(OUT_SIZE - 1):0] Y; 
  input  [(OUT_SIZE - 1):0] Z; 
  output [(OUT_SIZE - 1):0] R; 
  output [(OUT_SIZE - 1):0] G; 
  output [(OUT_SIZE - 1):0] B; 

  reg [(OUT_SIZE - 1):0] R;
  reg [(OUT_SIZE - 1):0] G;
  reg [(OUT_SIZE - 1):0] B;

  parameter CST_Red_X   =  65536; 
  parameter CST_Red_Z   =  91881; 
  parameter CST_Prec    =     16; //  16-bit (65536)

  parameter CST_Green_Y =  22553; 
  parameter CST_Green_Z =  46802; 

  parameter CST_Blue_Y  = 116130; 

  // Combined constants...
  parameter CST_OutSize = CST_Prec + OUT_SIZE + 2; 

  parameter CST_Offset_Red   = 188140487; 
  parameter CST_Offset_Green = 142071363;  
  parameter CST_Offset_Blue  = 237801046;

  // Define internal signals
  wire [(CST_OutSize - 1):0] RGB_X_KCM/* synthesis syn_keep=1 */; 	
  wire [(CST_OutSize - 1):0]   R_Z_KCM/* synthesis syn_keep=1 */; 
  wire [(CST_OutSize - 1):0]   G_Y_KCM/* synthesis syn_keep=1 */; 
  wire [(CST_OutSize - 1):0]   G_Z_KCM/* synthesis syn_keep=1 */; 
  wire [(CST_OutSize - 1):0]   B_Y_KCM/* synthesis syn_keep=1 */; 
  //
  reg [(CST_OutSize - 1):0]     Red_X_Z/* synthesis syn_preserve = 1 */;
  reg [(CST_OutSize - 1):0]    Red_full/* synthesis syn_preserve = 1 syn_noprune = 1*/; 
  reg [(CST_OutSize - 1):0] Green_cst_X/* synthesis syn_preserve = 1 */; 
  reg [(CST_OutSize - 1):0]   Green_Y_Z/* synthesis syn_preserve = 1 */; 
  reg [(CST_OutSize - 1):0]  Green_full/* synthesis syn_preserve = 1 syn_noprune = 1*/; 
  reg [(CST_OutSize - 1):0]    Blue_X_Y/* synthesis syn_preserve = 1 */; 
  reg [(CST_OutSize - 1):0]   Blue_full/* synthesis syn_preserve = 1 syn_noprune = 1*/; 


//  R = ROUND(X +   1.402 * Z - 2871.296)
//  G = ROUND(X - 0.34413 * Y - 0.71414 * Z + 2167.33696)
//  B = ROUND(X +   1.772 * Y - 3629.056)

  // ---------------------------------
  // Compute the Red component...
  // ---------------------------------
  const_mult #(OUT_SIZE, CST_OutSize, CST_Red_X)  Red_KCM_X(.Clock(Clock), .Reset(Reset), .Color(X), .Color_Out(RGB_X_KCM)); 

  const_mult #(OUT_SIZE, CST_OutSize, CST_Red_Z)  Red_KCM_Z(.Clock(Clock), .Reset(Reset), .Color(Z), .Color_Out(R_Z_KCM)); 

  // Adder for (X + Z)
  always @(posedge Clock or negedge Reset)
  begin : Red_X_Z_Adder
  	 if(!Reset)
	   Red_X_Z <= 0;
	 else
      Red_X_Z <= RGB_X_KCM + R_Z_KCM; 
  end 

  // Subtractor for Red => (X + Z) - CST_Offset_Red
  always @(posedge Clock or negedge Reset)
  begin : Red_Subt
    if(!Reset || (Red_X_Z <= CST_Offset_Red) )
	   Red_full <= 0;
	 else
	   Red_full <= Red_X_Z - CST_Offset_Red; 
  end 

  // ---------------------------------
  // Compute the Green component...
  // ---------------------------------
  const_mult #(OUT_SIZE, CST_OutSize, CST_Green_Y) Green_KCM_Y(.Clock(Clock), .Reset(Reset), .Color(Y), .Color_Out(G_Y_KCM)); 

  const_mult #(OUT_SIZE, CST_OutSize, CST_Green_Z) Green_KCM_Z(.Clock(Clock), .Reset(Reset), .Color(Z), .Color_Out(G_Z_KCM)); 

  // Adder for (X + constant)
  // Constant is also modified to perform rounding (+0.5)
  always @(posedge Clock or negedge Reset)
  begin : CST_X_Adder
    if(!Reset)
	   Green_cst_X <= 0;
	 else
      Green_cst_X <= RGB_X_KCM + CST_Offset_Green; 
  end 

  // Adder for Y + Z
  always @(posedge Clock or negedge Reset)
  begin : Green_Y_Z_Adder
    if(!Reset)
	   Green_Y_Z <= 0;
	 else
      Green_Y_Z <= G_Y_KCM + G_Z_KCM;
  end 

  // Subtractor for Green => (X + constant) - (Y + Z)
  always @(posedge Clock or negedge Reset)
  begin : Green_Subt
    if(!Reset || Green_cst_X < Green_Y_Z)
      Green_full <= 0;
    else
      Green_full <= Green_cst_X - Green_Y_Z;
  end 

  // ---------------------------------
  // Compute the Blue component...
  // ---------------------------------
  const_mult #(OUT_SIZE, CST_OutSize, CST_Blue_Y) Blue_KCM_Y(.Clock(Clock), .Reset(Reset), .Color(Y), .Color_Out(B_Y_KCM)); 

  // Adder for X + Y
  always @(posedge Clock or negedge Reset)
  begin : Blue_X_Y_Adder
    if(!Reset)
	   Blue_X_Y <= 0;
	 else
      Blue_X_Y <= RGB_X_KCM + B_Y_KCM;
  end 

  // Subtractor for Blue => (X + Y) - CST_Offset_Blue
  always @(posedge Clock or negedge Reset)
  begin : Blue_Subt
    if(!Reset || (Blue_X_Y <= CST_Offset_Blue))
      Blue_full <= 0; 
    else
      Blue_full <= Blue_X_Y - CST_Offset_Blue;
  end 

  // Limit and rounding: discard unwanted precision bits
  // Rounding already computed in result...	(256 -- 3760)
  always @(Red_full or Green_full or Blue_full)
  begin
    R = (Red_full[CST_OutSize - 1:CST_OutSize - OUT_SIZE - 2]   > 3760) ? 12'b1110_1011_0000 : (Red_full[CST_OutSize - 1:CST_OutSize - OUT_SIZE - 2]   < 256) ? 12'b0001_0000_0000 : Red_full  [(CST_OutSize - 3):(CST_OutSize - OUT_SIZE - 2)] ; // divide by 2^CST_Prec...
    G = (Green_full[CST_OutSize - 1:CST_OutSize - OUT_SIZE - 2] > 3760) ? 12'b1110_1011_0000 : (Green_full[CST_OutSize - 1:CST_OutSize - OUT_SIZE - 2] < 256) ? 12'b0001_0000_0000 : Green_full[(CST_OutSize - 3):(CST_OutSize - OUT_SIZE - 2)] ; // divide by 2^CST_Prec...
    B = (Blue_full[CST_OutSize - 1:CST_OutSize - OUT_SIZE - 2]  > 3760) ? 12'b1110_1011_0000 : (Blue_full[CST_OutSize - 1:CST_OutSize - OUT_SIZE - 2]  < 256) ? 12'b0001_0000_0000 : Blue_full [(CST_OutSize - 3):(CST_OutSize - OUT_SIZE - 2)] ; // divide by 2^CST_Prec...
  end

endmodule